Motorola Corporation

General Instrument Corporation

Malcolm Ryle Dwyer

Sek M Chai

Daniel Alan Linzmeier

Nikolaos Bellas

Ruei-Sung Lin

Nikos Bellas

Zhiyuan Li

James E Crenshaw

Erica M Lau

Nikolas Bellas

A method and apparatus for image processing a lens-distorted image (e.g., a fisheye image) is provided. The method includes partitioning coordinate points in a selected output image into tiles. The output image is an undistorted rendition of a subset of the lens-distorted image. Coordinate points on a border of the tiles in the output image are selected. For each tile, coordinate points in the lens-distorted image corresponding to each selected coordinate point in the output image are calculated. In addition, for each tile, a bounding box on the lens-distorted image is selected. The bounding box includes the calculated coordinates in the lens-distorted image. The bounding boxes are expanded so that they encompass all coordinate points in the lens-distorted image that map to all coordinate points in their respective corresponding tiles. Output pixel values are generated for each tile from pixel values in their corresponding expanded bounding boxes.

Method and apparatus for transforming a non-linear lens-distorted image

A specification of a configurable processor is generated by generating (1) specifications of first and second stream memory interfaces to be operable to access data in accordance with first and second stream descriptors, and (2) a specification of an interim data storage device (buffer) to be accessed by the first and second stream memory interfaces and to be operable to receive data from a first computational module via the first stream memory interface and to transfer data to a second computational module via the second stream memory interface. The specifications are output and may be used to configure a configurable processor.

Method and apparatus for configuring buffers for streaming data transfer

An array transform system for parallel computation of a plurality of elements of an array transform includes a memory for storing an array of data elements. Each column of data elements from the memory is copied to a shifter that shifts the column of data elements in accordance with a shift value to produce a shifted column of data elements. The shifted columns of data elements are accumulated in a plurality of accumulators, with each accumulator producing an element of the array transform. A controller controls the shift value dependent upon the position of the column of data elements in the array of data elements.

System and method for parallel computation of an array transform

A streaming data interface device () of a streaming processing system () is automatically generated by selecting a set of circuit parameters () consistent with a set of circuit constraints and generating () a representation of a candidate memory interface device based upon a set of stream descriptors. The candidate streaming data interface device is evaluated () with respect to one or more quality metrics and the representation of the candidate streaming processor circuit is output () if the candidate memory interface device satisfies a set of processing system constraints and is better in at least one of the one or more quality metrics than other candidate memory interface devices.

Automatic generation of streaming data interface circuit

A method and system for virtual memory translation of data represented in a multidimensional coordinate system when the physical memory may be located in more than one physical memory location. The translation of one or more virtual addresses into one or more accesses to one or more physical memories is achieved by representing each address of each element of a memory of the one or more physical memories as a point in a Cartesian coordinate system wherein consecutive points in the Cartesian coordinate system represent virtual memory addresses corresponding to elements from different physical memories of the one or more physical memories. Points in the Cartesian coordinate system are translated into one or more corresponding physical memory addresses, and read or write operations may be performed relative to these physical memory addresses. Multiple read or write operations may be performed during a single clock cycle through the use of parallel accesses of the one or more physical memories. Alternatively, multiple read or write operations may be performed in a pipelined architecture.

Virtual memory translation unit for multimedia accelerators

A programmable motion estimation module for processing pixel values from a sequence of digital video images. The module includes a programmable microcontroller, scalar and control register files, arithmetic logic units, a direct memory access unit and a vector array processor. The vector array processor includes a series of processing elements, a memory subsystem for storing pixel values and a crossbar switch for distributing pixel values from the memory subsystem to the processing elements. The module provides a flexible platform that can be programmed to implement a variety of different Motion Estimation (ME) algorithms using an associated Instruction Set Architecture without the need to modify the hardware.

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Glendale Heights, IL, United States of America

Malcolm Ryle Dwyer