Transmeta Corporation

Agate Logic, Inc.

Other

Adesto Technologies Corporation

Cswitch Corporation

Malcolm J Wing

Edmund Joseph Kelly

Robert F Cmelik

Ravi Sunkavalli

Godfrey P D'Souza

Colin Neal Murphy

Dana How

Jay B Patel

Brett Coon

John P Banning

Linus Torvalds

Arun Jangity

Jeffrey Schroeder

David Richard Trossen

Brian Choy

Patrick Gainer

Andrew Read

Douglas A Laird

Thomas E Stewart

Louis C Kordus

Ed McKernan

Robert K Yu

Ishai Naveh

David Roger Ditzel

Louis Charles Kordus, Ii

Grzegorz B Zyner

Pohrong Rita Chu

Ivo J Dobbelaere

Suresh Subramaniam

Mukunda Krishnappa

Jason Golbus

Dave Trossen

Kevin James

Colin B Hunter

A system can include a first memory section comprising a plurality of volatile memory cells; a second memory section comprising a plurality of nonvolatile memory cells; a first data path configured to transfer data between the first and second memory sections; an interface circuit coupled to receive access commands and address values, the interface circuit configured to determine if a data transfer operation is occurring in the device, and if the data transfer operation is occurring, accessing the address in the first memory section or accessing a location in the second memory section based on a select value, and if the data transfer operation is not occurring, accessing the address in the first memory section; and a compare circuit configured to compare a received address to a predetermined value to generate the select value.

System architectures with data transfer paths between different memory types

Structures and methods for improving logging in network structures are disclosed herein. In one embodiment, an apparatus can include: (i) a network interface card (NIC) configured to receive data, to transmit data, and to send data for logging; (ii) a memory log coupled to the NIC, where the memory log comprises non-volatile memory (NVM) configured to write the data sent for logging from the NIC; and (iii) where the data being sent for logging by the memory log occurs substantially simultaneously with the data being received by the NIC, and the data being transmitted from the NIC.

Network interface with logging

A system can include a first memory section comprising a plurality of volatile memory cells accessible via a first data path having a first bit width; a second memory section comprising a plurality of programmable impedance memory cells, each having at least one solid electrolyte layer; and a second data path configured to transfer data between the first and second memory sections independent of the first data path, the second data path having a greater bit width than the first data path.

System architecture with multiple memory types, including programmable impedance memory elements

Structures and methods for encoding data to reduce write cycles in a semiconductor memory device are disclosed herein. In one embodiment, a method of writing data to a semiconductor memory device can include: (i) determining a number of significant bits for data to be written in the semiconductor memory device; (ii) determining a tag associated with the data to be written in the semiconductor memory device, where the tag is determined based on the determined number of significant bits; (iii) encoding the data when the tag has a first state, where the tag is configured to indicate data encoding that comprises using N bits of the encoded data to store M bits of the data, where M and N are both positive integers and N is greater than M; and (iv) writing the encoded data and the tag in the semiconductor memory device.

Coding techniques for reducing write cycles for memory

A memory device can include a plurality of memory elements programmable between different impedance states; and circuits configured to apply first electrical conditions to one group of memory elements and second electrical conditions, different from the first electrical conditions, to another group of memory elements to vary a speed of an access operation to the different groups of memory elements.

Memory devices, circuits and, methods that apply different electrical conditions in access operations

A memory device can include a plurality of physical blocks that each include a number of memory elements programmable between at least two different impedance states, the memory elements being subject to degradation in performance; and bias circuits configured to applying healing electrical conditions to at least one spare physical block that does not contain valid data; wherein the healing electrical conditions are different from write operation electrical conditions, and reverse degradation of the memory elements of the at least one spare physical block.

A system for parsing frames including a first cell extraction circuit (CEC) configured to identify a first cell from a first frame, a first parser engine operatively connected to the first CEC, where the first parser engine is configured to generate a result based on the first cell, and a first forwarding circuit operatively connected to the first parser engine and configured to forward the result, where the first CEC, the first parser engine, and the first forwarding circuit are associated with a first frame parser unit.

System and method for parsing frames

A method of responding to an attempt to write a memory address including a target instruction which has been translated to a host instruction for execution by a host processor including the steps of marking a memory address including a target instruction which has been translated to a host instruction, detecting a memory address which has been marked when an attempt is made to write to the memory address, and responding to the detection of a memory address which has been marked by protecting a target instruction at the memory address until it has been assured that translations associated with the memory address will not be utilized before being updated.

Translated memory protection apparatus for an advanced microprocessor

Translated memory protection

A method and system of adaptive power control based on pre package characterization of integrated circuits. Characteristics of a specific integrated circuit are used to adaptively control power of the integrated circuit.

Adaptive power control based on pre package characterization of integrated circuits

A bus structure providing pipelined busing of data between logic circuits and special-purpose circuits of an integrated circuit, the bus structure including a network of pipelined conductors, and connectors selectively joining the pipelined conductors between the special-purpose circuits, other pipelined connectors, and the logic circuits.

High-bandwidth interconnect network for an integrated circuit

A configuration bit array including a hybrid electromechanical and semiconductor memory cell, and circuitry for addressing and controlling read, write, and erase accesses of the memory.

Non-volatile electromechanical configuration bit array

A multi-terminal electromechanical nanoscopic switching device which may be used as a memory device, a pass gate, a transmission gate, or a multiplexer, among other things.

Multi-terminal electromechanical nanocsopic switching device with control and release electrodes

Growing community of inventors

Menlo Park, CA, United States of America

Malcolm J Wing