Lucent Technologies Inc.

Agere Systems Guardian Corp.

Intel Corporation

Agere Systems Inc.

Marvellworld Trade Ltd.

Marvell International Limited

The Chase Manhattan Bank

Malcolm Harold Smith

Ronald David Javor

Eran Segev

Nir Binshtok

Douglas D Lopata

Ronald Lamar Freyman

Bruce W McNeill

John A Carelli, Jr

Gary H Weiss

Hongjiang Song

Ross Alan Kohler

Bart R McDaniel

Lysander Lim

Ernest Earl Woodward

Paul C Davis

Kevin William Glass

Ramin Khoini-Poorfard

Jiancheng Mo

H Scott Fetterman

Kirk B Ashby

Charles Raymond Miller

Mark K Lesher

Michael D Womac

Lysander B Lim

Valerie J Risk

Circuits, systems, and methods are disclosed for controlling multiple antenna receive paths in a wireless communication device. In some embodiments, the circuit may include a pair of receiving antennas, a first receive path including a VCO coupled to receive a PLL signal and a first mixer coupled to receive a first signal from the VCO and a signal from one of the antennas, and a second receive path integrated separately from the first receive path including a second mixer coupled to receive a second signal from the VCO and a signal from the other antenna. By utilizing the output of the VCO to tune the first and second mixers in the first and second receive paths to the same phase and frequency, control of the multiple antenna receive paths may be optimized.

Method and apparatus for downconverting a plurality of frequency modulated signals from a carrier frequency to baseband

Dual antenna system having one phase lock loop

A dual receive path for a wireless communication device having one synthesizer that drives one or two receive VCOs.

Structures and techniques for implementing multiple-antenna configurations within a radio frequency receiver are provided. In one aspect, a modularized multi-antenna receiver is provided having multiple independent microelectronic dice mounted on a common module substrate. In another aspect, a multi-antenna receiver is provided that utilizes at least one single ended low noise amplifier and at least one differential low noise amplifier within a common receiver.

Dual antenna receiver

A direct-down conversion receiver may include a transconductance-capacitor (GmC) filter to filter undesirable mixing products and provide a filtered baseband-differential signal. The GmC filter may include first and second transconductance-capacitor (GmC) circuits in series and a transconductance-feedback circuit in feedback with the second transconductance-capacitor circuit. The GmC circuits may comprise cross-coupled pairs of transistors to receive a baseband-differential signal and generate a differential output current. The GmC circuits may also comprise MOSCAPs coupled respectively between the differential inputs of the GmC circuit and internal-feedback nodes. In some embodiments, a substantially-constant bias voltage may be maintained across the voltage-dependent capacitors to allow the voltage-dependent capacitors to provide a substantially constant capacitance.

Direct down-conversion receiver with transconductance-capacitor filter and method

An amplifier includes a Darlington transistor pair and a biasing network to increase bias currents in an input transistor.

Biased Darlington transistor pair, method, and system

A loop filter for a frequency synthesizer provides a lower frequency pole with a smaller capacitor than conventional filters. The loop-filter comprises a resistor and a smaller capacitor in a series-feedback path, and a transconductor to sense a voltage across the resistor to either source or sink additional current proportional to the sensed voltage. The transconductor and the smaller capacitor may provide a larger capacitance. The loop filter also may comprise an operational amplifier having the smaller capacitor and the resistor in the series-feedback path to receive pulses from a charge pump. The filter may integrate the pulses and may generate a control voltage related to a width of the pulses.

Loop filter with active capacitor and method for generating a reference

An N-order sigma-delta analog-to-digital converter (ADC) system having multilevel quantized feedback. A multilevel quantized feedback stage incorporates a multibit, current-mode digital-to-analog converter (DAC). In one embodiment, reference current sources for the DAC may comprise a plurality of floating-gate MOS transistors so that analog nonvolatile precision linearity trimming of the feedback DAC may be accomplished. Calibration of the DAC may be performed at a relatively low refresh rate, for example, only at instances when the sigma-delta ADC system is activated.

Sigma-delta conversion with analog, nonvolatile trimmed quantized feedback

A system for two processors communicating though unidirectional links by embedding a strobe signal into the data by providing differential signals with different common mode signal levels.

Strobe through differential signaling

The present invention provides a method and apparatus for determining when an actual width of a resistor in an integrated circuit varies from a design width for that resistor due to process variations. The method and apparatus may be used to determine an actual amount of the process width variation. This amount may be used to effectively match resistors in an integrated circuit that do not have identical design width. The determination of process width variation in an integrated circuit may be used to match the bias resistor of a integrated current steering digital to analog converter to the converter's output resistors.

Apparatus and method for determining process width variations in integrated circuits

An electrical circuit which includes a filter bypass mode. The circuit includes an amplifier including an inverting terminal, a noninverting terminal and an output terminal, at least one first capacitor coupled to the inverting terminal of the amplifier through at least one first switch, and, at least one second capacitor coupled to the noninverting terminal of the amplifier through at least one second switch. The electrical circuit provides filtering when the first and second switches are in a first state, and when the first and second switches are in a second state, the electrical circuit provides substantially no filtering.

Tunable filter with bypass

A transmit portion of a WB-CDMA transceiver generates one or more spread data streams having values represented by a single bit, allowing for filtering of spread and combined data streams with a root raised cosine (RRC) filter employing single-bit multipliers. The RRC filter is a digital filter that i) employs multiplication of two values in which the length of at least one value is one bit; ii) is preferably implemented with muxs or a simple logic operator; and iii) may employ upsampling and modulation encoding of filter coefficients to reduce the coefficient length to, for example, one bit. The RRC filter may be an FIR filter having either one-bit or multi-bit coefficients, and apply RRC filtering to a spread user stream either before or after the spread user streams are combined. For some implementations, RRC filters are employed to filter each spread user stream prior to combining several processed user steams. For other implementations, the multi-bit valued data stream representing the combined user streams is upsampled to form an upsampled data stream of single-bit values, and RRC filtering is then applied to the upsampled data stream. Alternatively, implementations may use upsampled RRC filter coefficients that allow RRC filtering on the combined spread user streams represented as a sequence of multi-bit values.

Upsampling filter having one-bit multipliers for multiple spread-data streams

A baseband receiver particularly well-suited for wireless applications utilizes a dual-port DAC in a successive-approximation ADC, where the dual-port DAC replaces the separate pair of single port conventional DACs and is therefore shared by the I and Q down-converted components. The use of a dual-port DAC results in significant size and power savings over conventional arrangements.

Baseband receiver including dual port DAC

A phase shifter network receives at an input node an input clock signal which does not contain higher order harmonics and generates first and second phase-shifted clock signals which are 90&deg; apart and which have the same frequency as the input clock signal. First and second voltage comparators receive the first and second phase-shifted clock signals, respectively, and generates first and second squared clock signals, respectively, which are 90&deg; apart and which have the same frequency as the input clock signal. A combiner combines the first and second squared clock signals to produce an output clock signal having twice the frequency of the input clock signal.

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Macungie, PA, United States of America

Malcolm Harold Smith