Sandia Corporation

National Technology & Engineering Solutions of Sandia, LLC

Agere Systems Inc.

Socpra Sciences Et Genie S.e.c.

Noble Device Technologies Corporation

Malcolm Carroll

Jin K Kim

Clifford Alan King

Michael Joseph Cich

Aaron Gin

Phillip F Marsh

Erik W Young

Jeffrey Devin Bude

John King Gamble, Iv

Anand Ganti

Ezra Bussmann

Jeff Devin Bude

Rajib Rahman

James Ewers Levy

Gregory A Ten Eyck

Stephen M Carr

Wayne Witzel

Noah Tobias Jacobson

Michel Pioro-Ladrière

Martin Rudolph

Nathaniel Bishop

Sophie Rochette

Erik Nielsen

John King Gamble

Robin J Blume-Kohout

Andrew J Landahl

Michael Lilly

Khoi Thi Nguyen

A quantum dot structure having a split-gate geometry is provided. The quantum dot is configured for incorporation into a quantum dot array of a quantum processing unit. A gap between a reservoir accumulation gate and a quantum dot accumulation gate provides a tunnel barrier between an electric charge reservoir and a quantum dot well. An electrical potential applied to the gates defines a tunnel barrier height, width and charge tunneling rate between the well and the reservoir without relying on any barrier gate to control the charge tunneling rate.

Electronic circuit for control or coupling of single charges or spins and methods therefor

A silicon metal-oxide semiconductor device transports a spin-polarized single electron. An array of silicon quantum dot electrodes is arranged atop a silicon dioxide layer of a silicon metal-oxide semiconductor. The array comprises at least a first electrode and a second electrode adjacent to the first electrode. A transport control logic for individually controls a voltage applied to the electrodes. The transport control logic is configured to gradually decrease a voltage at the first electrode while gradually increasing a voltage at the second electrode. Localization of the single electron is adiabatically transferred from the first electrode to the second electrode while maintaining a desired energy gap between a ground state and a first excited state of the single electron.

Electron spin-based information shuttling for a computer system

A quantum computing device that includes a plurality of semiconductor adiabatic qubits is described herein. The qubits are programmed with local biases and coupling terms between qubits that represent a problem of interest. The qubits are initialized by way of a tuneable parameter, a local tunnel coupling within each qubit, such that the qubits remain in a ground energy state, and that initial state is represented by the qubits being in a superposition of |0&#x3e; and |1&#x3e; states. The parameter is altered over time adiabatically or such that relaxation mechanisms maintain a large fraction of ground state occupation through decreasing the tunnel coupling barrier within each qubit with the appropriate schedule. The final state when tunnel coupling is effectively zero represents the solution state to the problem represented in the |0&#x3e; and |1&#x3e; basis, which can be accurately read at each qubit location.

Semiconductor adiabatic qubits

An infrared focal plane array (FPA) is disclosed which utilizes a strained-layer superlattice (SLS) formed of alternating layers of InAs and InGaSb with 0&#x2266;x&#x2266;0.5 epitaxially grown on a GaSb substrate. The FPA avoids the use of a mesa structure to isolate each photodetector element and instead uses impurity-doped regions formed in or about each photodetector for electrical isolation. This results in a substantially-planar structure in which the SLS is unbroken across the entire width of a 2-D array of the photodetector elements which are capped with an epitaxially-grown passivation layer to reduce or eliminate surface recombination. The FPA has applications for use in the wavelength range of 3-25 &#x3bc;m.

Strained layer superlattice focal plane array having a planar structure

A photodetector for detecting infrared light in a wavelength range of 3-25 &#x3bc;m is disclosed. The photodetector has a mesa structure formed from semiconductor layers which include a type-II superlattice formed of alternating layers of InAs and InGaSb with 0&#x2266;x&#x2266;0.5. Impurity doped regions are formed on sidewalls of the mesa structure to provide for a lateral conduction of photo-generated carriers which can provide an increased carrier mobility and a reduced surface recombination. An optional bias electrode can be used in the photodetector to control and vary a cut-off wavelength or a depletion width therein. The photodetector can be formed as a single-color or multi-color device, and can also be used to form a focal plane array which is compatible with conventional read-out integrated circuits.

Lateral conduction infrared photodetector

A method is disclosed for isolating single atoms of an atomic species of interest by locating the atoms within silicon nanocrystals. This can be done by implanting, on the average, a single atom of the atomic species of interest into each nanocrystal, and then measuring an electrical charge distribution on the nanocrystals with scanning capacitance microscopy (SCM) or electrostatic force microscopy (EFM) to identify and select those nanocrystals having exactly one atom of the atomic species of interest therein. The nanocrystals with the single atom of the atomic species of interest therein can be sorted and moved using an atomic force microscope (AFM) tip. The method is useful for forming nanoscale electronic and optical devices including quantum computers and single-photon light sources.

Isolating and moving single atoms using silicon nanocrystals

Strained-layer superlattice focal plane array having a planar structure

A method of making a semiconductor device having a predetermined epitaxial region, such as an active region, with reduced defect density includes the steps of: (a) forming a dielectric cladding region on a major surface of a single crystal body of a first material; (b) forming a first opening that extends to a first depth into the cladding region; (c) forming a smaller second opening, within the first opening, that extends to a second depth greater than the first depth and that exposes an underlying portion of the major surface of the single crystal body; (d) epitaxially growing regions of a second semiconductor material in each of the openings and on the top of the cladding region; (e) controlling the dimensions of the second opening so that defects are confined to the epitaxial regions grown within the second opening and on top of the cladding region, a first predetermined region being located within the first opening and being essentially free of defects; (f) planarizing the top of the device to remove all epitaxial regions that extend above the top of the cladding layer, thereby making the top of the first predetermined region grown in the second opening essentially flush with the top of the cladding region; and (g) performing additional steps to complete the fabrication of the device. Also described are unique devices, such as photodetectors and MOSFETs, fabricated by this method, as well as unique contacting configurations that enhance their performance.

Semiconductor devices with reduced active region defects and unique contacting schemes

A method of making a semiconductor device having a predetermined epitaxial region, such as an active region, with reduced defect density includes the steps of: (a) forming a dielectric cladding region on a major surface of a single crystal body of a first material; (b) forming a first opening that extends to a first depth into the cladding region; (c) forming a smaller second opening, within the first opening, that extends to a second depth greater than the first depth and that exposes an underlying portion of the major surface of the single crystal body; (d) epitaxially growing regions of a second semiconductor material in each of the openings and on the top of the cladding region; (e) controlling the dimensions of the second opening so that defects are confined to the epitaxial regions grown within the second opening and on top of the cladding region, a first predetermined region being located within the first opening and being essentially free of defects; (D planarizing the top of the device to remove all epitaxial regions that extend above the top of the cladding layer, thereby making the top of the first predetermined region grown in the second opening essentially flush with the top of the cladding region; and (g) performing additional steps to complete the fabrication of the device. Also described are unique devices, such as photodetectors and MOSFETs, fabricated by this method, as well as unique contacting configurations that enhance their performance.

Growing community of inventors

Albuquerque, NM, United States of America

Malcolm Carroll