Intel Corporation

Maksim Lukoshkov

Weigang Li

Junyuan Wang

Kaijie Guo

Yao Huo

Ned M Smith

Sanjay Kumar

Xin Zeng

Tomasz Kantecki

Liang J Ma

Songwu Shen

Laurent Coquerel

Zijuan Fan

Sanjay K Kumar

Examples described herein relate to a device including circuitry to permit or deny the device to write-to or read-from kernel space memory of a virtualized execution environment by use of multiple process identifiers. In some examples, the device is communicatively coupled with the virtualized execution environment in a manner consistent with one or more of: Single Root IO Virtualization (SR-IOV), Scalable I/O Virtualization (SIOV), or PCI express (PCIe). In some examples, to control write or read operations to kernel space memory of a virtualized execution environment by the device by use of multiple process identifiers, the circuitry is to perform an address translation based on a first process identifier and second process identifier associated with the virtualized execution environment.

Technologies to provide access to kernel and user space memory regions

Techniques and mechanisms for determining an operation to be performed with a direct memory access (DMA) request. An inspection unit () is coupled between an input-output memory management unit (IOMMU) () and an endpoint device (). The inspection unit () stores a registry () comprising entries () which each correspond to a respective address, and a respective one or more resources of the endpoint device (). A given entry () of the registry () is created based on a message from the IOM MU () which indicates the successful completion of an address translation to facilitate a DMA request. The endpoint device () performs a search, based on a DMA request, to determine if any registry () entry () indicates a combination of an address and an endpoint resource, where said combination matches a corresponding combination indicated by the DMA request. Communication of the DMA request to the IOMMU () is contingent on a result of the search.

Device, system, and method for inspecting direct memory access requests

Examples herein relate to a system that includes a first memory device; a second memory device; and an input-output memory management unit (IOMMU). The IOMMU can search for a virtual-to-physical address translation entry in a first table for a received virtual address and based on a virtual-to-physical address translation entry for the received virtual address not being present in the first table, search a second table for a virtual-to-physical address translation entry for the received virtual address, wherein the first table is stored in the first memory device and the second table is stored in the second memory device. In some examples, based on a virtual-to-physical address translation entry for the received virtual address not being present in the second table, a page table walk is performed to determine a virtual-to-physical address translation for the received virtual address. In some examples, the first table includes an IO translation lookaside buffer (IOTLB).

Address translation technologies

Growing community of inventors

Clarecastle, Ireland

Maksim Lukoshkov