Kabushiki Kaisha Toshiba

Makoto Yoshimi

Yukihito Oowaki

Masako Yoshida

Shigeru Kawanaka

Naoyuki Shigyo

Mamoru Terauchi

Akira Nishiyama

Takashi Yamada

Tsuneaki Fuse

Osamu Arisumi

Kazuya Ohuchi

Tomohisa Mizuno

Tomoaki Shino

Kazumi Inoh

Hideaki Nii

Minoru Takahashi

Sadayuki Yoshitomi

Takeshi Hamamoto

Satoshi Inaba

Tohru Ozaki

Yukihiro Ushiku

Atsushi Murakoshi

Masami Aoki

Yoshiaki Matsushita

Kazuya Matsuzawa

Masao Iwase

Ryuji Ohba

Yutaka Ishibashi

Hiroyoshi Tanimoto

Akira Toriumi

Hitomi Kawaguchiya

Sanae Fukuda

Tetsunori Wada

A semiconductor device includes a semiconductor layer used as a substrate formed on an insulating film, a plurality of MOS transistors arranged on the semiconductor layer and each having a gate, a source, and a drain, a pair of MOS transistors of the plurality of MOS transistors constituting a detection circuit for detecting magnitudes of potentials applied to the gates as a difference between conductances of the pair of transistors, and a diffusion layer region of the same conductivity type as that of the semiconductor layer, arranged on one of portions of the sources and drains of the pair of MOS transistors constituting the detection circuit, for connecting portions serving as the substrates of the pair of MOS transistors to each other.

Semiconductor memory device including a pair of MOS transistors forming a detection circuit

In a bipolar transistor improved to exhibit an excellent high-frequency property by decreasing the width of the intrinsic base with without increasing the base resistance, an emitter region, intrinsic base region and collector region are closely aligned on an insulating layer, and the intrinsic base region and the collector region make a protrusion projecting upward from the substrate surface. The protrusion has a width wider than the width of the intrinsic base region.

Lateral bipolar transistor formed on an insulating layer

Method of manufacturing semiconductor memory device

In a lateral bipolar transistor, its emitter region, base region, link base region, and so forth, are made in self alignment with side walls of masks by using partly overlapping two mask patterns. Therefore, not relying on the mask alignment accuracy, these regions are made in a precisely controlled positional relation. Thus, the lateral bipolar transistor, thus obtained, is reduced in parasitic resistance of the base and parasitic junction capacitance between the emitter and the base, and alleviated in variance of characteristics caused by fluctuation of the length of a link base region, length of the emitter-base junction and relative positions of the emitter and the collector, and can be manufactured with a high reproducibility.

Method for manufacturing a lateral bipolar transistor

Semiconductor memory device

A semiconductor device comprises: a first semiconductor layer 6 having a first conductivity formed on a substrate having a surface of an insulating material 4; a source region 16a and a drain region 16b, which are formed on the first semiconductor layer so as to be separated from each other and which have a second conductivity different from the first conductivity; a channel region 6 formed on the first semiconductor layer between the source region and the drain region; a gate electrode 10 formed on the channel region a gate sidewall 14 of an insulating material formed on a side of the gate electrode; and a second semiconductor layer 18 having the first conductivity formed on at least the source region. This semiconductor device can effectively suppress the floating-body effect with a simple structure.

Semiconductor device and manufacturing method thereof

The present invention provides a semiconductor device which includes a substrate having a projection-shaped semiconductor element region, a gate electrode formed through a gate insulating film on the upper face and side face of the element region, and a first conductivity type source region and drain region provided in a manner to form a channel region on the upper face of the element region across the gate electrode, and which has a high concentration impurity region containing a second conductivity type impurity at a concentration higher than that on the surface of the channel region in the central part of the projection-shaped semiconductor element region.

Semiconductor device having a projecting element region

A semiconductor device having a MISFET includes: a silicon substrate (2) having a semiconductor region on a surface thereof; a source region (10a) and a drain region (10b) formed in the semiconductor region separately; a channel region formed in the semiconductor region and between the source region and the drain region; a gate electrode (6) formed on the channel region; and a region (8a) formed of Si.sub.1-x C.sub.x overlapping the source region and having a carbon concentration enough to increase an energy gap therein beyond that in the channel region. Further, the MISFET is constructed in such a way that a hetero-junction surface formed between the region formed of Si.sub.1-x C.sub.x (8a) and the other portion of the semiconductor region on the side of the channel region exists at an interface between the source region (10a) and the channel region or in the vicinity thereof, in order to realize a high speed operation, even if the device is microminiaturized.

Semiconductor device and manufacturing method therefor

A structure of a semiconductor device and a method of manufacturing the same is provided wherein a leakage current can be reduced while improving a drain breakdown voltage of an Insulated-Gate transistor such as a MOSFET, MOSSIT and a MISFET, and a holding characteristic of a memory cell such as a DRAM using these transistors as switching transistors can be improved, and further a reliability of a gate oxide film in a transfer gate can be improved. More particularly, a narrow band gap semiconductor region such as Si.sub.x Ge.sub.1-x, Si.sub.x Sn.sub.1-x, PbS is formed in an interior of a source region or a drain region in the SOI.IG-device. By selecting location and/or mole fraction of the narrow band gap semiconductor region in a SOI film, or selecting a kind of impurity element to compensate the crystal lattice mismatching due to the narrow-bandgap semiconductor region, the generation of crystal defects can be suppressed. Further the structure that the influences of the crystal defects to the transistor or memory characteristics such as the leakage current can be suppressed, even if the crystal defects are generated, are also proposed.

Insulated-gate transistor having narrow-bandgap-source

In a semiconductor device having a thin SOI film, the thickness of a semiconductor layer formed on an insulating film is so adjusted as to be less than a maximum distance allowable to complete depletion of the layer. While the thickness of a channel region is adjusted to be less than that of impurity-diffusion regions. Further, the insulating layer is so formed to have a thicker portion under the channel region, and thinner portions under the source region and the drain region as the impurity-diffusion regions. The semiconductor layer has steps at the boundaries between the channel region and the impurity-diffusion regions, and the top face of the channel region is arranged so as to be lower than the top faces of the impurity-diffusion regions. A region having a width less than the maximum depletion distance and an impurity concentration larger, than that of the channel region and less than that of the drain region is formed between the channel region and the drain region.

Semiconductor device having a single crystal semiconductor layer formed

A semiconductor memory device, in particular a dynamic random access memory cell which realizes a high speed thereof and presenting a superior controllability. The dynamic random access memory (DRAM) cell includes: a first transistor; a second transistor, electrically connected in series to the first transistor, for storing an electric charge, the second transistor including a portion for erasing the charge stored at the second transistor, wherein the first transistor and the second transistor are electrically connected between a power line and a bit line; and a diode electrically connected between the first transistor and the second transistor. Alternatively, the present invention can be realized with three transistors where the memory cell includes: a first transistor and a second transistor provided between the power line and the bit line in a manner that the first and second transistors are connected in series at a connecting node therebetween; and a third transistor provided between a gate of the first transistor and the connecting node, wherein a gate of the second transistor and a gate of the third transistor are commonly connected to the word line.

High-speed semiconductor gain memory cell with minimal area occupancy

On the surface of an insulating substrate, a semi-conductor layer composed of a semiconductor layer of a first conductivity type on which a high-concentration semiconductor layer of the first conductivity type is formed. By selectively etching the semiconductor layer, the high-concentration external base region of the first conductivity is left, and at the same time, only a thicker prospective internal base region just under the external base region and a prospective emitter region and prospective collector region, which are located on both sides of the prospective internal base region and have steps between themselves and the prospective internal base region, are left to form island regions. A sidewall insulating film is formed which covers at least the sidewalls on the prospective collector region side among sidewalls of the external base region and sidewalls at the steps of the prospective internal base region adjoining the sidewalls of the external base region. The emitter region and collector region of the second conductivity type are formed by ion implantation perpendicular to the substrate with the insulating film covering the external base region and the sidewall insulating film as blocking mask.

Manufacturing method of semiconductor devices

A CMOS inverter circuit incorporating a P channel MOSFET and an N channel MOSFET, both of which can achieve surface conduction, is provided while maintaining the prescribed miniaturization. Thus, the threshold value and conductance of the both MOSFETs are independent of the thickness of the silicon film, and can be easily controlled in the manufacturing processes thereof.

Semiconductor device

Growing community of inventors

Tokyo, Japan

Makoto Yoshimi