Fujitsu Corporation

Makoto Yanagisawa

Yukinori Kodama

Yoshihiro Takemae

Hirohiko Mochizuki

Junji Ogawa

Masao Taguchi

Hiroyoshi Tomita

Atsushi Hatakeyama

Takaaki Suzuki

Hideaki Kawai

Masao Nakano

Yasuhiro Fujii

Kimiaki Sato

Nobumi Kodama

Yasuhiro Takada

Toshiya Uchida

Yasurou Matsuzaki

Masataka Mizukoshi

Tsuyoshi Higuchi

Jun Funakoshi

Shigeki Nozaki

Toshitaka Mizuguchi

Shinnosuke Kamata

Kazuyuki Kanazashi

Kazumi Kojima

Seiji Yamagata

Hidehiko Akasaki

Takashi Horii

Hatsuo Miyahara

Yuji Kurita

Toyonobu Yamada

Masami Matsuoka

Katsumi Shigenobu

Tomoharu Oka

Satoshi Momozono

Takeo Takematsu

A circuit for stabilizing an electric current includes a constant voltage supplying circuit configured to supply a constant voltage, and a current generating circuit coupled to the constant voltage supplying circuit to generate an electric current based on a predetermined voltage responsive to the constant voltage and to adjust a current amount of the electric current to a predetermined amount by feedback control based on comparison of the predetermined voltage with a voltage appearing across a predetermined resistance responsive to the electric current.

Current stabilization circuit, current stabilization method, and solid-state imaging apparatus

A semiconductor memory device capable of conducting test operations includes a plurality of word drivers which keep word lines in an active state when the word drivers are selected until the word drivers are reset. The semiconductor memory device further includes a control circuit which successively selects more than one of the plurality of word drivers so as to achieve simultaneous activation of word lines corresponding to selected ones of the plurality of word drivers during the test operations.

Semiconductor memory device capable of multiple word-line selection and method of testing same

A semiconductor device includes a one-shot pulse generating circuit that generates a one-shot pulse having a predetermined pulse width at a rise or fall timing of a first clock signal, a cycle time measuring circuit that measures a cycle-time of the first clock signal from the one-shot pulse output from the one-shot pulse generating circuit, an internal clock generating circuit that generates a second clock signal based on the cycle time measured by the cycle time measuring circuit and the one-shot pulse output from the one-shot pulse generating circuit. The second clock signal has a cycle time identical to the first clock signal and has a rise or fall timing which is advanced by a specific time than that of the first clock signal, and the specific time is obtained by subtracting the cycle time of the first clock signal from a predetermined time, and a data output circuit that outputs data after a predetermined delay time from the rise or fall timing of the second clock signal.

Semiconductor device

A semiconductor integrated circuit includes a plurality of circuits operating in parallel in accordance with a timing signal and having an enabled state and a disabled state, a control circuit setting each of the plurality of circuits to the enable state or the disabled state in accordance with an operation mode, and a timing adjustment circuit which adjusts the timing signal in accordance with a number of circuits which are in the enabled state.

Semiconductor integrated circuit

A semiconductor wafer testing method includes a pre-test step for forming a temporary test film on a surface of a semiconductor wafer, a test step for testing the semiconductor wafer by applying a probe to the temporary test film and a post-test step for exfoliating the temporary test film from the surface of the semiconductor wafer. The temporary test film includes test electrode groups each provided with a plurality of regularly arranged test electrodes, and wiring patterns for electrically connecting the test electrodes with corresponding ones of semiconductor unit electrodes in respective semiconductor units on the semiconductor wafer. Probe pins of said probe are arranged so as to be aligned with corresponding ones of the test electrodes of the respective test electrode groups.

Semiconductor wafer testing method with probe pin contact

A semiconductor device includes a one-shot pulse generating circuit that generates a one-shot pulse having a predetermined pulse width at a rise or fall timing of a first clock signal, a cycle time measuring circuit that measures a cycle time of the first clock signal from the one-shot pulse output from the one-shot pulse generating circuit, an internal clock generating circuit that generates a second clock signal based on the cycle time measured by the cycle time measuring circuit and the one-shot pulse output from the one-shot pulse generating circuit. The second clock signal has a cycle time identical to the first clock signal and has a rise or fall timing which is advanced by a specific time than that of the first clock signal, and the specific time is obtained by subtracting the cycle time of the first clock signal from a predetermined time, and a data output circuit that outputs data after a predetermined delay time from the rise or fall timing of the second clock signal.

Semiconductor memory device capable of multiple word-line selection and

A semiconductor device includes a one-shot pulse generating circuit that generates a one-shot pulse having a predetermined pulse width at a rise or fall timing of a first clock signal, a cycle time measuring circuit that measures a cycle time of the first clock signal from the one-shot pulse output from the one-shot pulse generating circuit, an internal clock generating circuit that generates a second clock signal based on the cycle time measured by the cycle time measuring circuit and the one-shot pulse output from the one-shot pulse generating circuit. The second clock signal has a cycle time identical to the first clock signal and has rise or fall timing which is advanced by a specific time than that of the first clock signal, and the specific time is obtained by subtracting the cycle time of the first clock signal from a predetermined time, and a data output circuit that outputs data after a predetermined delay time from the rise or fall timing of the second clock signal.

A semiconductor circuit has a first transistor, a second transistor, a third transistor, and a fourth transistor. The first and fourth transistors are a first conduction type, and the second and third transistors are a second conduction type opposite to the first conduction type. The semiconductor circuit employs a first power supply line for supplying a first voltage, a second power supply line for supplying a second voltage, and a third power supply line for supplying a third voltage outside of the range determined by the first voltage and the second voltage. The first, second, and third transistors are connected in series between the second power supply line and the third power supply line, and the fourth transistor is connected between an input terminal and a control electrode of the first transistor.

Semiconductor circuit having MOS circuit for use in strong electric field

A semiconductor memory device includes a memory cell array in which a number of sense amplifiers are provided, a plurality of segmented drive lines each connected to a group of sense amplifiers for driving the same, each of the segmented drive lines being formed of first and second drive line segments forming a pair, and a number of trunks for supplying electric power to the segmented drive lines. Each of the trunks includes a first conductor strip extending from a first side of the memory cell array toward a second side for connection to a plurality of the first drive line segments upon crossing the same, and a second conductor strip extending from the second side of the memory cell array toward the first side for connection to a plurality of the second drive line segments upon crossing the same. The first and second conductor strips have distal end parts having a reduced width and a mutually complementary shape, such that the first and second conductor strips are disposed to form a straight strip having a substantially constant width throughout the memory cell array.

Semiconductor memory device having a capability for controlled

A method of making an SDRAM (synchronous dynamic random access memory) into either a low-speed type or a high-speed type includes the steps of determining an electrical connection of a predetermined electrode of the SDRAM, and providing the predetermined electrode with a voltage level defined by the electrical connection, the voltage level determining whether the SDRAM is made into the low-speed type or the high speed type, wherein the low-speed type can carry out consecutive writing operations at a low clock rate for two addresses having the same row address, and the high-speed type can carry out simultaneous writing operations at a high clock rate for two addresses having the same row address and consecutive column addresses.

Semiconductor memory device and method of forming the same

A semiconductor memory having a plurality of banks, a first specify unit, and a second specify unit. The first specify unit is used to specify one of the banks by decoding a bank address signal contained in a row address signal. The second specify unit is used to specify one of the banks by decoding the bank address signal contained in the row address signal, according to bank status signals that indicate whether or not each of the banks is activated. Therefore, the semiconductor memory is used for different bank configurations. Namely, with this arrangement, the semiconductor memory is capable of serving as a memory having a smaller number of banks, to thereby improve convenience.

Semiconductor memory having a plurality of banks usable in a plurality

In a word line driving circuit coupled to a word line of a memory cell array of a semiconductor memory device, a first transistor has a first terminal receiving an input signal based on a row address signal applied to the semiconductor memory device, a second terminal, and a control terminal receiving a first timing signal. A second transistor having a first terminal receiving a second timing signal, a second terminal connected to the word line, and a control terminal connected to the second terminal of the first transistor. A third transistor has a first terminal connected to the second terminal of the second transistor, a second terminal set at a predetermined potential, and a control terminal receiving a third timing signal. The first transistor has a threshold voltage less than that of at least one of the second and third transistors.

Word line driving circuit and semiconductor memory device using the same

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Kawasaki, Japan

Makoto Yanagisawa