Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Makoto Yamakura

Katsumi Adachi

Tadashi Kobayashi

Yoshinori Kobayashi

Yoshiyuki Mochizuki

Kunio Sekimoto

Kenji Nishimura

Akio Nishimura

Hitoshi Araki

Yudai Ishibashi

Akira Uesaki

Kazutaka Nishio

Kazu Segawa

Provided is a graphics rendering device that includes a frame data generation unit, access pattern setting unit, and frame data writing unit. The frame data generation unit generates, from part of stencil data, a part of frame data composed of a piece of second pixel information corresponding to a predetermined number of pixels in accordance with a first access pattern and an anti-alias pattern used in generating pieces of second pixel information. The access pattern setting unit sets, in accordance with the first access pattern and the anti-alias pattern, a second access pattern indicating pieces of second pixel information accessible by a single access to the frame buffer. The frame data writing unit writes in the frame buffer, when the frame data generation unit has generated a number of pieces of second pixel information indicated by the second access pattern, a part of the frame data corresponding to the number of pieces of second pixel information in accordance with the second access pattern.

Graphics rendering device, graphics rendering method, graphics rendering program, recording medium with graphics rendering program stored thereon, integrated circuit for graphics rendering

An image generation device includes a memory in which a burst length, which is the smallest unit of read/write processing, is large; and an image generation device in which processing efficiency at the time of a memory access does not decrease, even in the case of accessing a rendering buffer for rendering a polygon. Image data is stored in a rendering buffer in block units made up of plural pixels, and image data of pixels corresponding to the polygon is stored in a serial region of the rendering buffer. A valid pixel flag indicating that a valid pixel is present within the block is stored in the rendering information buffer. The rendering buffer is accessed as little as possible based on placement of the valid pixel flags within the block.

Image generation device and image generation method

A curved surface image processing apparatusaccording to the present invention that can render an object at higher speed and in higher quality by performing image processing using NURBS data includes: a data input unitfor receiving NURBS data; a coordinate transformation unitfor performing coordinate transformation on NURBS data; an animation control unitfor controlling animation data of each frame to be rendered; a data transformation unitfor transforming NURBS data into rational Bezier data; a patch division unitfor subdividing a rational Bezier surface patch; a normal determination unitfor calculating normals of control points of a divided surface patch; a perspective transformation unitfor performing perspective transformation on a divided surface patch; and a rendering unitfor rendering a surface patch.

Curved surface image processing apparatus and curved surface image processing method

The present invention provides a method of driving an active matrix display device in which one frame comprises a plurality of sub-frames each comprising a write time and a hold time and gray scale driving is brought about by the cumulative effect of the hold times. Gray scale display driving is carried out by randomly scanning scan lines other than one predetermined scan line in a predetermined sequence in the hold time of each sub-frame corresponding to the one predetermined scan line so that any one sub-frame is not written to any one scan line more than once and one frame is such that in each of the scan lines, the writings and the hold time of each of the sub-frames is ensured to bring about gray scale display. Through this means, the frame period is shortened.

Active matrix display device and method of driving the same

The motion circuit of the present invention is an on-board driver circuit which is composed of polycrystal silicon semiconductor layers formed on a substrate, and which is provided with a first latch circuit for latching one of a normal phase and reverse phase clock signals having a clock skew using a clock signal and for outputting it to a shift register, and a second latch circuit for latching the other one of the normal phase and reverse phase clock signals using a clock signal and for outputting to the shift register. The latch operations of the first and second latch circuits are timed to make the two clock signals have reverse polarities. Consequently, it is realized to provide a motion circuit performing stable circuit operations without malfunctions, by preventing the occurrence of the fail phenomenon due to a skew between the normal phase and reverse phase clock signals which drive the shift register. It is also realized to provide an on-board driver circuit for a liquid crystal display panel by employing the motion circuit.

Motion circuit and on-board driver circuit for liquid crystal display panel employing the motion circuit

Growing community of inventors

Osaka, Japan

Makoto Yamakura