Renesas Electronics Corporation

Renesas Technology Corp.

Taiwan Semiconductor Manufacturing Comp. Ltd.

Makoto Yabuuchi

Koji Nii

Shinji Tanaka

Yuta Yoshida

Yasumasa Tsukamoto

Yuichiro Ishii

Hidehiro Fujiwara

Shigeki Ohbayashi

Masao Morimoto

Yohei Sawada

Noriaki Maeda

Ken Shibata

Toshiaki Sano

Nobuhiro Tsuda

Takeshi Okagaki

Koji Shibutani

Yoshisato Yokoyama

Kengo Masuda

Yoshikazu Saito

Kazutami Arimoto

Daisuke Oshida

Takeshi Sunada

Motoki Tamura

A memory driver includes a word line driver circuit, a reference circuit, and a bias circuit. The word line driver circuit is coupled to a word line and configured to selectively provide a reference voltage from a reference node to the word line according to an input signal. The reference circuit has a capacitor coupled to the reference node. The reference circuit is configured to store the reference voltage on the capacitor and lower the reference voltage from a first voltage level to a second voltage level when the reference voltage is provided by the word line driver circuit from the reference node to the word line. The bias circuit coupled to the reference node and configured to regulate the reference voltage at the reference node by the second voltage level.

Memory driver, memory system, and operating method

The plurality of CAM cells MC are configured to discriminate a match or mismatch between stored data stored in advance and search data. A match line is coupled to a plurality of CAM cells, and has a voltage level controlled based on discrimination results of the plurality of CAM cells. A first transistor and a second transistor are coupled in series between a common match output line and a predetermined power source. The first transistor is controlled to be turned ON or OFF based on a voltage level of the match line, and the second transistor is controlled to be turned ON or OFF by a search enabling signal asserted at the time of a search operation.

Semiconductor device having a contents addressable memory

A semiconductor device including an SRAM capable of sensing a defective memory cell that does not satisfy desired characteristics is provided. The semiconductor device includes a memory cell, a bit line pair being coupled to the memory cell and having a voltage changed towards a power-supply voltage and a ground voltage in accordance with data of the memory cell in a read mode, and a specifying circuit for specifying a bit line out of the bit line pair. In the semiconductor device, a wiring capacitance is coupled to the bit line specified by the specifying circuit and a voltage of the specified bit line is set to a voltage between a power voltage and a ground voltage in a test mode.

Semiconductor device

A semiconductor device includes a plurality of memory cells connected to a match line; a word line driver connected to a word line; a valid cell configured to store a valid bit indicating valid or invalid of an entry; a first precharge circuit connected to one end of the match line and configured to precharge the match line to a high level; and a second precharge circuit connected to the other end of the match line and configured to precharge the match line to a high level. The plurality of memory cells are arranged between the first precharge circuit and the second precharge circuit, and the second precharge circuit is arranged between the word line driver and the plurality of memory cells.

Semiconductor device including a content reference memory

A semiconductor device that can reduce power consumption while improving the accuracy of learning and inference is provided. The semiconductor device is connected to data lines PBL, NBL, and comprises a product operation memory cellfor storing data of ternary value and performing a product-sum operation between a stored data and an input data INP and a data in the data lines PBL, NBL.

Along with the miniaturization of the semiconductor memory device, the resistor and parasitic capacitance of the wires become large, which prevents the semiconductor memory device from being speeded up. In a semiconductor memory device having a semiconductor substrate having a main surface, a first memory cell row having a plurality of first memory cells arranged in parallel to a first direction in plan view on the main surface, a first word line connected to the plurality of first memory cells, a first word line driver for changing a potential of the first word line, and a control circuit for outputting a first predecode signal to the first word line driver via the first predecode line in response to a clock signal and an address signal, a repeater is inserted between the control circuit and the first word line driver.

Semiconductor memory device

A semiconductor device includes a first wiring having a first portion, a second portion, a third portion provided between the first portion and the second portion, memory cells connected to the third portion of the first wiring, a field effect transistor having a drain connected to the second portion, and a gate, and a second wiring provided in parallel with the first wiring. The third portion of the first wiring includes a fourth portion located nearest to the first portion and a fifth portion located nearest to the second portion. The first wiring further includes a sixth portion disposed between the first portion and the fourth portion. The memory cells include a first memory cell connected to the fourth portion and a second memory cell connected to the fifth portion. The second wiring is electrically connected between the sixth portion and the gate of the field effect transistor.

Semiconductor device and method of driving semiconductor device

A semiconductor device capable of improving operating margins is provided. The semiconductor device comprises a memory circuit including a memory cell comprised of a SOTB transistor, and a mode designation circuit switching operation modes of the memory circuit for a first mode or a second mode. The memory circuit includes a substrate bias generation circuit supplying a substrate bias voltage to the SOTB transistor and a timing signal generation circuit generating a timing signal used for a reading operation or a writing operation of the memory circuit. The substrate bias generation circuit does not supply the substrate bias voltage to the SOTB transistor in the second mode.

A TCAM (Ternary Content Addressable Memory) according to the embodiment includes repeaters in a delay path for controlling the timing in the replica circuit that defines the timing of matching. According to the above configuration, the TCAM which consumes low power and operates at high speed can be realized.

Content addressable memory

A semiconductor device includes a plural search memory cells, a plural match lines, a plural sub-ground lines, and a plural amplifiers. The search memory cells are disposed in a matrix form. The match lines are disposed in association with respective memory cell rows and used to determine whether search data matches data stored in the search memory cells. The sub-ground lines are disposed in association with respective memory cell rows. The amplifiers are disposed in association with respective memory cell rows to amplify the potentials of the match lines. The match lines and the sub-ground lines are respectively precharged to a first potential and a second potential before a data search. When the search data is mismatched, the match lines are electrically coupled to associated sub-ground lines through the search memory cells and set to an intermediate potential that is intermediate between the first potential and the second potential.

A semiconductor device includes a semiconductor substrate, a first well region formed on the semiconductor substrate, a first fin integrally formed of the semiconductor substrate on the first well region and extended in a first direction in a plan view, a first electrode formed on the first fin via a first gate insulating film, and extended in a second direction crossing the first direction in the plan view, a tap region formed on the semiconductor substrate adjacent to the first well region in the second direction, and supplying a first potential to the first well region, a second fin integrally formed of the semiconductor substrate on the tap region and extended in the first direction in the plan view, and a first wiring layer formed on the second fin in a portion overlapping the tap region in the plan view.

A semiconductor device includes a semiconductor substrate, a memory cell formed on the semiconductor substrate, a word line connected to the memory cell, and an auxiliary line connected to the word line.

An area of a semiconductor device having a FINFET can be reduced. The drain regions of an n-channel FINFET and a p-channel FINFET are extracted by two second local interconnects from a second Y gird between a gate electrode and a dummy gate adjacent thereto, to a third Y grid adjacent to the second Y gird. These second local interconnects are connected by a first local interconnect extending in the X direction in the third Y grid. According to such a cell layout, although the number of grids is increased by one because of the arrangement of the first local interconnect, the length in the X direction can be reduced. As a result, the cell area of the unit cell can be reduced while a space between the first and second local interconnects is secured.

An object of the present invention is to provide a highly-reliable content addressable memory. Provided is a content addressable memory including: a plurality of CAM cells; a word line joined to the CAM cells; a plurality of bit lines joined to the CAM cells; a plurality of search lines joined to the CAM cells; a match line joined to the CAM cells; a match amplifier joined to the match line; and a selection circuit that can select the output of the match amplifier in accordance with the value of the word line.

Provided is a semiconductor memory device having a low power consumption write assist circuit. The semiconductor memory device includes multiple word lines, multiple bit line pairs, multiple memory cells, multiple auxiliary line pairs, a write driver circuit, a write assist circuit, and a select circuit. The memory cells are coupled to the word lines and the bit line pairs in such a manner that one memory cell is coupled to one word line and one bit line pair. The auxiliary line pairs run parallel to the bit line pairs in such a manner that one auxiliary line pair runs parallel to one bit line pair. The select circuit couples, to the write driver circuit, one bit line pair selected from the bit line pairs in accordance with a select signal, and couples, to the write assist circuit, an associated auxiliary line pair running parallel to the selected bit line pair.

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Tokyo, Japan

Makoto Yabuuchi