Kabushiki Kaisha Toshiba

Semiconductor Technology Academic Research Center

Kioxia Corporation

Material Concept, Inc.

Makoto Wada

Akihiro Kajita

Tadashi Sakai

Yuichi Yamazaki

Tatsuro Saito

Atsuko Sakata

Atsunobu Isobayashi

Masayuki Kitamura

Kazuyuki Higashi

Masayuki Katagiri

Naoshi Sakuma

Junichi Koike

Takamasa Usui

Ichiro Mizushima

Hideki Shibata

Naofumi Nakamura

Noriyoshi Shimizu

Noriaki Matsunaga

Yumi Hayashi

Masaki Yoshimaru

Tsuneo Uenaka

Hayato Nasu

Satoshi Nishikawa

Shingo Takahashi

Mariko Suzuki

Kei Watanabe

Hiroshi Toyoda

Shinichi Nakao

Hisao Miyazaki

Taishi Ishikura

Yosuke Akimoto

Kazuya Ohuchi

Yuji Sutou

Hiroko Miki

Daisuke Ando

Naohsi Sakuma

Yousuke Akimoto

According to one embodiment, a method for manufacturing a semiconductor device is disclosed. The method includes forming a co-catalyst layer and catalyst layer above a surface of a semiconductor substrate. The co-catalyst layer and catalyst layer have fcc structure. The fcc structure is formed such that (111) face of the fcc structure is to be oriented parallel to the surface of the semiconductor substrate. The catalyst includes a portion which contacts the co-catalyst layer. The portion has the fcc structure. An exposed surface of the catalyst layer is planarized by oxidation and reduction treatments. A graphene layer is formed on the catalyst layer.

Method for manufacturing a semiconductor device

A solar cell module capable of preventing the occurrence of a PID failure in a solar photovoltaic power generation system with a MW capacity, said system being used in a high-temperature high-humidity environment; and a method for manufacturing this solar cell module. A solar cell module which comprises a protection glass material and a sealing material on a light receiving surface side of a substrate, and which also comprises an oxide layer between the substrate and the protection glass material, said oxide layer containing a metal element and silicon. It is preferable that the oxide layer contains at least one metal element selected from the group consisting of magnesium, aluminum, titanium, vanadium, chromium, manganese, zirconium, niobium and molybdenum. It is also preferable that the oxide layer has a refractive index of from 1.5 to 2.3 (inclusive) with respect to incident light having a wavelength of 587 nm.

Solar cell module and method for manufacturing the same

According to one embodiment, a semiconductor device is disclosed. The device includes interconnects each including a catalyst layer and a graphene layer thereon. The catalyst layer includes a first to fifth catalyst regions arranged along a first direction in order of the first to fifth catalyst regions. The first, third and fifth catalyst regions include upper surfaces higher than those of the second and fourth catalyst regions. Adjacent ones of the first to fifth catalyst regions are in contact with each other. A distance between the first and the third catalyst region and a distance between the third and fifth catalyst region are greater than a mean free path of graphene. The graphene layer includes a first graphene layer on the second catalyst region and a second graphene layer on the fourth catalyst region.

Semiconductor device and method of manufacturing the same

According to one embodiment, a semiconductor device is disclosed. The device includes a foundation layer including first and second layers being different from each other in material, and the foundation layer including a surface on which a boundary of the first and second layers is presented, a catalyst layer on the surface of the foundation layer, and the catalyst layer including a protruding area. The device further includes a graphene layer being in contact with the protruding area.

Semiconductor device including catalyst layer and graphene layer thereon and method for manufacturing the same

A wire of an embodiment includes: a substrate; a metal film provided on the substrate; a metal part provided on the metal film; and graphene wires formed on the metal part, wherein the graphene wire is electrically connected to the metal film, and the metal film and the metal part are formed using different metals or alloys from each other.

Wire and semiconductor device

According to one embodiment, a semiconductor device includes a catalyst underlying layer formed on a substrate including semiconductor elements formed thereon and processed in a wiring pattern, a catalyst metal layer that is formed on the catalyst underlying layer and whose width is narrower than that of the catalyst underlying layer, and a graphene layer growing with a sidewall of the catalyst metal layer set as a growth origin and formed to surround the catalyst metal layer.

Semiconductor device comprising a graphene wire

According to one embodiment, a semiconductor device includes a metal interconnect and a graphene interconnect which are stacked to one another.

A semiconductor device according to one embodiment includes: a semiconductor substrate provided with a semiconductor element; a first conductive member formed on the semiconductor substrate; a first insulating film formed on the same layer as the first conductive member; a second conductive member formed so as to contact with a portion of an upper surface of the first conductive member; a second insulating film formed on the first insulating film so as to contact with a portion of the upper surface of the first conductive member, and including at least one type of element among elements contained in the first insulating film except Si; and an etching stopper film formed on the second insulating film so as to contact with a portion of a side surface of the second conductive member, and having an upper edge located below the upper surface of the second conductive member.

Semiconductor device and method of fabricating the same

According to one embodiment, a graphene interconnection includes an insulating film, a catalyst film, and a graphene layer. An insulating film includes an interconnection trench. A catalyst film is formed in the interconnection trench and filling at least a portion of the interconnection trench. A graphene layer is formed on the catalyst film in the interconnection trench, and including graphene sheets stacked in a direction perpendicularly to a bottom surface of the interconnection trench.

Graphene interconnection and method of manufacturing the same

A conductive film of an embodiment includes: a fine catalytic metal particle as a junction and a graphene extending in a network form from the junction.

Conductive film and semiconductor device

According to one embodiment, a graphene interconnection includes a first insulating film, a first catalyst film, and a first graphene layer. A first insulating film includes an interconnection trench. A first catalyst film is formed on the first insulating film on both side surfaces of the interconnection trench. A first graphene layer is formed on the first catalyst film on the both side surfaces of the interconnection trench, and including graphene sheets stacked in a direction perpendicularly to the both side surfaces.

According to one embodiment, a semiconductor device using multi-layered graphene wires includes a substrate having semiconductor elements formed therein, a first graphene wire formed above the substrate and including a multi-layered graphene layer having a preset impurity doped therein, a second graphene wire formed on the same layer as the first multi-layered graphene wire above the substrate and including a multi-layered graphene layer into which the preset impurity is not doped, a lower-layer contact connected to the undersurface side of the first multi-layered graphene wire, and an upper-layer contact connected to the upper surface side of the second multi-layered graphene wire.

Interconnection of semiconductor device with graphene wire

Growing community of inventors

Yokohama, Japan

Makoto Wada