Panasonic Corporation

Matsushita Electric Industrial Co., Ltd.

Makoto Tsutsue

Masaki Utsumi

Nobuo Eda

Masahiko Ogawa

Ken Nishimura

Akiko Ishida

Kotaro Nomura

Kazushige Kinoshita

A seal ring structure is formed through a multilayer structure of a plurality of dielectric films in a peripheral part of a chip region to surround the chip region. A dual damascene interconnect in which an interconnect and a plug connected to the interconnect are integrated is formed in at least one of the dielectric films in the chip region. Part of the seal ring structure formed in the dielectric film in which the dual damascene interconnect is formed is continuous. A protection film formed on the multilayer structure has an opening on the seal ring. A cap layer connected to the seal ring is formed in the opening.

Semiconductor device

A semiconductor device includes an interlayer dielectric with a single-layer structure having a plurality of pores. The porosity of the interlayer dielectric per unit volume varies in a thickness direction.

Semiconductor device and method for fabricating the same

An electronic device has an element formed in the chip region of a substrate, a plurality of interlayer insulating films formed on the substrate, a wire formed in the interlayer insulating films in the chip region, and a plug formed in the interlayer insulating films in the chip region and connecting to the wire. A seal ring extending through the plurality of interlayer insulating films and continuously surrounding the chip region is formed in the peripheral portion of the chip region. A stress absorbing wall extending through the plurality of interlayer insulating films and discretely surrounding the seal ring is formed outside the seal ring.

Electronic device and method for fabricating the same

In a method of manufacturing a semiconductor device which method is made up of a process of forming a wiring groove using a hard mask, a metal hard maskis used to form a wiring groove, allowing the shape of the wiring grooveto be stabilized. Furthermore, a part or all of the metal hard maskis removed before the formation of TaN and Cu layers in the wiring groove. This enables a reduction in possible damage, which may increase the dielectric constant of the surface of low-dielectric-constant film, and thus in possible inter-wire leakage current. As a result, a reliable semiconductor device can be provided.

Method of manufacturing semiconductor device

A semiconductor device includes: a semiconductor substrate; a first insulating film (third insulating film) formed on the semiconductor substrate, having a first trench (second interconnect trench), and having a composition ratio varying along the depth from an upper face of the first insulating film; and a first metal interconnect (second metal interconnect) filling the first trench (second interconnect trench). The mechanical strength in an upper portion of the first insulating film (third insulating film) is higher than that in the other portion of the insulating film (third insulating film).

Method for fabricating a semiconductor device that includes processing an insulating film to have an upper portion with a different composition than an other portion

A semiconductor device includes an element formed on a substrate, at least one insulating film formed on the substrate, and a seal ring formed in the insulating film so as to surround a region where the element is formed and to extend through the insulating film. The semiconductor device further includes a void region including a void and formed in the insulating film in a region located outside the seal ring when viewed from the element.

Growing community of inventors

Shiga, Japan

Makoto Tsutsue