Kabushiki Kaisha Komatsu Seisakusho

Komatsu Corporation

Makoto Takebe

Masao Hagiwara

Masakazu Moritoki

Yukinori Katayama

A digital phase synchronizing apparatus delays sequentially a clock signal output from an oscillator, generates a plurality of delayed clock signals, selects a delayed clock signal that is synchronized with horizontal synchronizing signal HS from among the delayed clock signals using a change point detection circuit, and selects the output signal. Meanwhile, fine delay circuit further delays sequentially the selected delayed clock signal, generates a plurality of delayed clock signals, and selects a delayed clock signal that corresponds to the setting of a rotary dip switch as the system clock, thereby to efficiently acquire phase synchronization of the clock signal with the input signal without being affected by the signal characteristics of the input signal.

Digital phase synchronizing apparatus

Provided is an image synthesizing device with which a specific display region P of a sub-image is synthesized and displayed within a specific display region Q of a main image displayed on a display , wherein this image synthesizing device comprises a frame memory with which the data in the synthesis and display region P out of the sub-image data is continuously stored in the order of input, after which the stored sub-image data is read out when the scanning address of the main image data is an address corresponding to the display region Q, and a selector with which the main image data displayed on the display and the sub-image data continuously and sequentially read out from the frame memory are inputted, and when the scanning address of the main image data is an address corresponding to the display region Q, the selected channel is switched from main image data to the sub-image data and outputted to the display where this sub-image data is displayed, which allows the capacity of the frame memory used for image synthesis to be smaller, and allows the sub-image to be reduced or magnified at the desired scale factor.

Image synthesizing device and image conversion device for synthesizing and displaying an NTSC or other interlaced image in any region of a VCA or other non-interlaced image

A display control device for displaying data stored in a video memory on a flat display such as an EL or liquid crystal display on the basis of display control signals output from a CRT control device, which comprises a memory means that allows data read and write operations to be executed simultaneously and that has a capacity to store at least one screen of display data for display on the flat display and display control means for alternately executing, in accordance with the display control signals, a first operation in which data corresponding to an upper half of the display screen are retrieved from the data stored in the video memory and sequentially output to an upper region of the display, data corresponding to the upper half of the display screen are sequentially stored in the memory means, and data corresponding to a lower half of the display screen stored in the memory means are sequentially output to a lower region of the display, and a second operation in which data corresponding to the lower half of the display screen are retrieved from the data stored in the video memory and sequentially output to the lower region of the display, data corresponding to the lower half of the display screen are sequentially stored in the memory means, and data corresponding to the upper half of the display screen stored in the memory means are sequentially output to the upper region of the display

Display control device

For arithmetically combining the values of two numbers, for example adding and subtracting, comprising a data deletion system for deleting values from input data and outputting the result. The system has a deletion number detection apparatus for finding a value on the basis of input data and output data, wherein an output data number setting device sets the bits of an output data number to be all '1' in logical value prior to sending that number to a down counter which subtracts the output number from the input number for the result.

Binary subtraction device

An image data memory control unit for storing the image data of a plurality of planes in a multiport video memory including a memory component having a random port for reading and writing data therethrough in response to input address signals and a register component having a serial port for outputting data that have been stored in the memory component serially in sequence from the lower address in synchronicity with input clock signals, comprises an image processor for outputting address signals in which the most significant bit portion is a plane recognition bit portion that recognizes the plurality of planes, and for outputting the image data of the plurality of planes therethrough to the multiport video memory in response to the address signals; and address conversion unit for converting the address signals output from the image processor so that the plane recognition bit portion is moved to the least significant bit portion, and the remaining bits are shifted to higher significant bits following the least significant bit portion.

Image data memory control unit

A serial controller in which nodes to which are connected one or plurality of sensors and one or a plurality of actuators are connected in series in the form of a closed loop including a main controller which sends data frame signals including a first special code, a second special code and output data for the actuators. The main controller measures and controls the time interval for sending the data frame signals and selecting a broken-line detection time setting in order to improve the transmission efficiency and to carry out the control in real time.

Growing community of inventors

Hiratsuka, Japan

Makoto Takebe