Kabushiki Kaisha Toshiba

Adv Antest Corporation

Makoto Tabata

Koichi Sato

Akihiro Tsujimura

Shoji Kato

Masaomi Nakahata

Minoru Sakurai

Jun Morimoto

Tomoko Honda

Satoru Honda

Yoshikazu Hata

Nobuyoshi Kuroiwa

Shinya Sato

Ippei Kashiwagi

Noboru Okino

Ko Katsurahara

Sato Koichi

One embodiment is a communication device in which different wireless systems whose frequency bands are close to each other are installed. For a first wireless system, a first antenna using a first frequency band is provided. For a second wireless system, a second antenna using a second frequency band is provided. The first frequency band is set in a range wider than the second frequency band. The second frequency band is included in a part of the range of the first frequency band. An imaginary surface extending along the first antenna and an imaginary surface extending along the second antenna cross each other on their extension lines.

Communication device and smart meter

A wireless device includes: a casing having a first face; a display configured to be visible from the first face; a touch sensor formed by a transparent material and mounted in the casing with respect to the display as a part of the first face; a substrate mounted to a side opposite to the first face with respect to the display; and an antenna element including: a first portion built in the casing, connected to a feeding point included in the substrate, and located within a first range occupied by the touch sensor when viewed from a direction perpendicular to the first face; and a second portion located within a second range other than the first range.

Wireless device

An electronic apparatus includes: a first molded body; a second molded body which composes housing with the first molded body; a first conductive pattern provided in the housing; a second conductive pattern provided on an outer surface of the housing; and a first conductive member. The first conductive member passes through a gap of a mating face between the first molded body and the second molded body. The first conductive member connects the first conductive pattern and the second conductive pattern.

Electronic apparatus

A control apparatus controlling testing of a memory under test that includes one or more row repair memory blocks and column repair memory blocks. The control apparatus comprises a counting section that sequentially receives test results respectively indicating pass/fail of a plurality of test blocks of the memory under test, and sequentially counts, for each first-type memory block, which is a row-oriented memory block or a column-oriented memory block, a fail memory block number among second-type memory blocks; a selecting section that selects memory blocks first-type memory blocks for which the fail memory block number exceeds a reference value, such that the number of selected memory blocks is no greater than the number of first-type repair memory blocks of the memory under test; and a test control section that masks test blocks among the memory blocks selected by the selecting section and causes further testing of the memory under test.

Control apparatus and control method

An electronic apparatus includes: a first molded body; a second molded body which composes a housing with the first molded body; a first conductive pattern provided on an outer surface of the first molded body; a second conductive pattern provided in the housing; and a first conductive pin. The first conductive pin passes through the first molded body and connects the first conductive pattern and the second conductive pattern.

Provided is a test apparatus that tests a device under test having a test function for sequentially outputting, from a single test terminal, signals that would be output from a plurality of terminals, the test apparatus comprising: a test section that supplies the device under test with a test signal and receives signals that are sequentially output from the test terminal in response to the test signal; an identifying section that identifies a correspondence between each signal sequentially received by the test section and a signal that would be output from one of the terminals of the device under test; and a counting section that counts a number of signals judged to be unacceptable from among the signals sequentially received by the test section for each terminal of the device under test, based on the correspondence identified by the identifying section.

Test apparatus that tests a device under test having a test function for sequentially outputting signals

An electronic apparatus includes: a housing provided with a first conductive pattern; a substrate provided with a first wiring layer in a surface thereof and fixed to the housing; and a first conductive member connecting the first conductive pattern and the first wiring layer. The first conductive pattern extends onto an outer surface and an inner surface of the housing. The first conductive member is in contact with each of at least a part of the first conductive pattern extending onto the inner surface and an end of the first wiring layer. Alternatively, an electronic apparatus includes: a housing provided with a conductive pattern and having a through part in a frame portion thereof; and a substrate provided with a wiring layer on a surface thereof and having a protruding part and fixed to the housing. The protruding part and the through part are fit. The conductive pattern extends onto an outer surface of the housing and onto an inner surface of the through part. At least some of the conductive pattern extending onto the inner surface is in contact with an end of the wiring layer.

An electronic device includes a first molded body having a first frame, the first molded body being provided with a conductive pattern on its outer surface, a second molded body having a second frame, the second molded body being joined to the first molded body, a wiring sheet made of an insulative sheet provided with an interconnection pattern, a circuit board having a feed point, and a feed line having a first end extended to a mating surface of the first frame opposed to the second frame and a second end connected to the conductive pattern. The interconnection pattern has a first end connected to the one end of the feed line. The interconnection pattern has a second end connected to the feed point.

Electronic device and method for manufacturing same

The disclosure concerns a semiconductor tester for testing a MUT, comprising a pattern generator; a pattern formatter; a comparator comparing a result signal from the MUT with an expectation value; a bad block memory; an AFM pre-storing pass/fail information of each of memory cells; a data compressor compressing data of pass/fail information in the AFM; a compression failure buffer memory storing data compressed; a good block register storing an address number of a good block prepared; and an address generator, wherein when the block to be compressed is a good one, the good block register sends a address number of the good block to the compress failure buffer memory.

Semiconductor testing device and method of testing semiconductor memory

A memory block is subject to an erasure operation by a batch operation. Subsequently, a read-out test is conducted upon the memory block to count the number of unerased memory cells. If the count F is equal to or greater than a given number T , a plurality of erasure operations are conducted consecutively next. If F <T , a single erasure operation is conducted next, subsequently followed by a read-out test. The erasure operations and the read-out tests are repeated.

Growing community of inventors

Tokyo, Japan

Makoto Tabata