Mitsubishi Denki Kabushiki Kaisha

Renesas Technology Corp.

Makoto Suwa

Hiroshi Miyamoto

Tadaaki Yamauchi

Shigeru Mori

Junko Matsumoto

Takeo Okamoto

Zengcheng Tian

Hideki Yonetani

Tsutomu Nagasawa

Yoshikazu Morooka

Shigeru Kikuda

Mitsuya Kinoshita

Tetsuichiro Ichiguchi

Shinichi Jinbo

Kiyohiro Furutani

Kozo Ishida

Hideto Hidaka

Kenichi Yasuda

Michihiro Yamada

A manner of generating internal voltages such as a high voltage, an intermediate voltage and an internal power supply voltage is switched in accordance with a power supply level setting signal. When the voltage level of an external power supply voltage is low, a current drive transistor receiving an output of a comparing circuit and an auxiliary drive transistor are forcedly set in a conductive state, and external power supply voltage is transmitted on an internal power supply line. At this time, the comparing operation of the comparing circuit is stopped. When the level of the external power supply voltage is high, the comparing circuit is activated down convert the external power supply voltage for generating a peripheral power supply voltage on the internal power supply line.

Semiconductor device having internal voltage generated stably

Data pad regions are arranged in four divided regions of a semiconductor memory chip of a rectangular shape, respectively, and data pads are selectively utilized in each of the four divided regions in accordance with a word structure. Thus, it is possible to implement a semiconductor memory chip capable of being assembled in both a single chip package and a multi chip package.

Semiconductor circuit device adaptable to plurality of types of packages

The semiconductor memory device includes a refresh timer for determining a refresh cycle of self-refresh operation. The refresh timer includes a voltage regulator, a ring oscillator and a counter. The voltage regulator generates a bias voltage having positive temperature characteristics. The ring oscillator varies an oscillation cycle of a pulse signal according to the bias voltage. The counter counts a prescribed number of pulse signals and generates a refresh signal for executing refresh operation. The semiconductor memory device thus varies the refresh cycle according to a temperature change, and executes refresh operation with an appropriate refresh cycle.

Semiconductor memory device requiring refresh operation

An input circuit includes a gate circuit receiving an output power supply voltage that determines the logic level of an input signal or a comparison circuit receiving an input signal and a reference voltage depending on the output power supply voltage supplied from a pad different from a power supply pad for an output circuit. Even if the output power supply voltage varies to cause the input signal to change, whether the input signal is at H level or L level can accurately be determined and an internal signal is generated correctly

Semiconductor device adaptable to a plurality of kinds of interfaces

A row address decoder of a semiconductor memory device generates internal row address signals RAD< and /RAD< > by switching most significant bit and least significant bit of row address signals RA< > and /RA< > that correspond to address signals A to A , respectively. In a twin cell mode, the least significant bits RAD< > and /RAD< > of the internal row address signals corresponding to the most significant bits RA< > and /RA< > of the row address signal that are not used are selected simultaneously by row address decoder, and two adjacent word lines are activated simultaneously. Consequently, the configuration of memory cell in the semiconductor memory device can electrically be switched from the normal single memory cell type to the twin memory cell type.

Semiconductor memory device switchable to twin memory cell configuration

A clock buffer of a DRAM includes: a first NAND gate which is driven by a first internal power supply voltage (2.5 V) and which determines the level of an input clock signal if the DRAM is used for a TTL-system interface (MLV&equals;2.5 V); and a second NAND gate which is driven by a second internal power supply voltage (1.8 V) and which determines the level of the input clock signal if the DRAM is used for a 1.8 V-system interface (MLV&equals;0 V). Accordingly, in each of the first and second NAND gates, sizes of four MOS transistors can be set at optimum values, respectively.

Semiconductor device used in two systems having different power supply voltages

A semiconductor memory device includes banks, predecoders, a latch circuit, a counter, a fuse and buffers. The bank includes a plurality of memory cells arranged in rows and columns, and others. The predecoders are disposed in a central portion of the semiconductor memory device. The predecoder produces a predecode signal for selecting each of the banks based on a bank address received from the buffer, and outputs the predecode signal to the banks. The predecoder produces the predecode signal for selecting each of the banks based on the bank address, and outputs the predecode signal to the banks. Consequently, interconnections in the central portion can be reduced in number.

Semiconductor memory device allowing high density structure or high performance

Pad lines are placed on the peripheral region of a chip along EAST band and WEST band (E/W band). In order to allow the chip with pads arranged on the peripheral region to be adaptable to a TSOP, VDD and VSS pads are arranged on the edge region on NORTH band and SOUTH band (N/S band) near the center of the N/S band. Moreover, in consideration of frame design for the TSOP, some pads on the ends of the pad lines among the pads included in the pad lines are arranged in reverse order relative to the order of pins. Further, VDDQ and VSSQ pads are arranged in the same order as that of pins for a package which requires no consideration of frame design. On the other hand, for use in a BGA package, VDD and VSS pads are arranged in pairs at respective ends of the pad lines. A semiconductor memory device with this pad arrangement is accordingly adaptable to various types of packages.

Semiconductor memory device adaptable to various types of packages

A well region is provided on a doped semiconductor layer. A resistor element is formed on the well region and a fixed voltage level is applied. A parasitic capacitance is formed between the well region and the resistor and a noise generated at one end of the resistor is compensated for or filtered by the parasitic capacitance.

Semiconductor device including resistance element with superior noise

In a level generating circuit 1 included in an internal power supply circuit of a DRAM, MOS transistors 14 and 16 for inactivating a V.sub.1 generating circuit 3, and MOS transistors 23 and 25 for inactivating a V.sub.2 generating circuit 5 are provided. When V.sub.1 is to be adjusted, V.sub.2 generating circuit 5 is inactivated, and when V.sub.2 is to be adjusted, V.sub.1 generating circuit 3 is inactivated. Therefore, failure of adjustment of internal power supply potential intVcc caused by confusion of V.sub.1 and V.sub.2 can be prevented.

Semiconductor device and method of adjusting internal power supply

A semiconductor memory device 251 has a sense amplifier 7 of shared sense amplifier type. A switching signal generating circuit 253 is provided for application of control signals .phi..sub.1 and .phi..sub.2 to a control electrode of a connection transistor of sense amplifier 7. Switching signal generating circuit 253 applies control signals .phi..sub.1 and .phi..sub.2 which is boosted only for a prescribed time period after the rise of external /RAS signal to the control electrode of the connection transistor of sense amplifier 7. Therefore, as compared with the operation in which control signals .phi..sub.1 and .phi..sub.2 which are constantly boosted are applied, power consumption can be reduced.

Semiconductor memory device allowing reduction of power consumed in a

A semiconductor memory device includes a plurality of memory blocks, i main row or column select lines extending over the plurality of memory blocks, and a decoder for selecting one of the main row or column select lines in accordance with an applied address signal. The decoder includes i outputs. Each of the memory blocks includes a plurality of memory cells arranged in rows and columns and at least (i+1) sub row or column select lines each for selecting one row or one column of memory cells. A shift redundancy circuit is provided for each of the memory blocks, for connecting the main row or column select line and the sub row or column select line. The shift redundancy circuit includes a switch circuit for connecting one main row or column select line to one of the plurality of adjacent sub row or column select lines, and a circuit for setting a connection path of the switch circuit. The shift redundancy circuit connects successively adjacent sub row or column select lines to main row or column select lines in one to one correspondence except a defective sub row or column select line associated with a defective bit.

Redundancy circuit for repairing defective bits in semiconductor memory

In a general read out operation, data read out from a memory cell array is amplified by a preamplifier group. The amplified data is provided to a selector unit. The selector unit responds to a bit organization select signal to select data according to a predetermined bit configuration. The selected data is provided to a data bus. In a test mode, the selector unit responds to a test mode signal to provide a test result to a data bus corresponding to a predetermined bit organization. Therefore, only the required data bus is used according to the bit organization and the test mode.

Semiconductor memory device carrying out input and output of data in a

A semiconductor device according to the present invention includes on the main surface of a p substrate a storing circuit region and peripheral circuit regions. An n well surrounds a p well including the storing circuit region and a p well including the peripheral circuit regions. As a result, a capacitance element is formed in the semiconductor substrate. It is possible to miniaturize the semiconductor device, and to improve reliability of connection between elements.

Semiconductor device and manufacturing method thereof

A semiconductor memory device includes a memory array. The bit line pairs of the odd number order in the memory array belong to a first group, and the bit line pairs of the even number order belong to a second group. A first amplifier is connected to each bit line pair. Corresponding to the first group, write buses read buses and a read/test circuit are provided. Corresponding to the second group, write buses read buses and a read/test circuit are provided. A column decoder selects a plurality of bit line pairs simultaneously at the time of testing. At the time of testing, each of the read/test circuits compares data read out from the plurality of bit line pairs belonging to the corresponding group with a given expected data for providing the comparison result.

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Hyogo, Japan

Makoto Suwa