Matsushita Electric Industrial Co., Ltd.

Makoto Sube

Toshiyuki Sano

Misa Kasahara

Masaki Kobayashi

Haruo Kogane

Kenji Tabei

Hidetoshi Mimura

Jun Ebisawa

Yuichiro Takahashi

Masayuki Kamiya

An inventive video camera imager supports an interlace scan mode, a dynamic range-widening scan (WS) mode and a sequential scan mode with a limited amount of circuitry. For this, a WS image signal of 2N lines and a sequential scan image signal of 2N lines (N is the number of scan lines of an image to be obtained) is used. Every other line of WS image signal is longer in exposure time than adjacent lines of the WS image signal. A simplified imager may support only interlace scan mode and sequential scan mode, or may support only WS mode and sequential scan mode.

Video camera imager and imager IC capable of plural kinds of double-image processings

A period for a long-term exposure signal is discriminated from a period for a short-term exposure signal. Based on a discrimination signal, an AGC gain selector switches a set value for the gain and a knee point selector switches a set value for the knee point, thereby independently controlling the gain and the knee point for each of the long-term exposure signal and the short-term exposure signal.

Solid state imaging apparatus for a video camera capable of independently performing a knee point adjustment and a gain control

An imaging apparatus includes a CCD for accumulating an image signal by an n-times long-time-accumulation (n is an integer of &ldquo;1&rdquo; or more); a timing control circuit for controlling to read out the image signal accumulated in the CCD according to the n-times long-time-accumulation; a memory for storing the read-out image signal for one frame period or more; and a recursive noise reduction circuit for performing a noise reduction process on the basis of the image signal read out from the CCD and the one-frame-period-or-more delayed image signal read out from the memory. In case of the 2n-times long-time-accumulation, in a vertical scanning period in which the image signal is output from the CCD, the image signal from the recursive noise reduction circuit is written to the memory. On the other hand, in a vertical scanning period in which the image signal is not output from the CCD, the writing of the image signal generated by the recursive noise reduction circuit to the memory is inhibited, and the image signal is output as an output signal as it is.

Imaging apparatus

Low illuminance shooting is achieved by raising the gain or sensitivity through noise reduction while mitigating the deterioration in resolution. An image signal that has been imaged by CCD and amplified CDS is converted into a series of digital pixel values. A weighted moving average of a current pixel value and pixel values of at least two pixels spatially adjacent to the pixel of the current pixel value are calculated. The weighted moving average is divided by a division factor smaller than the sum of weights used in the weighted moving average calculation. If the image signal is smaller than a predetermined value, a selector supplies the divided weighted moving average as the current pixel value to the next stage. This enables not only a gain increase due to noise reduction but also a mitigation of the deterioration in resolution.

Imaging apparatus with low-illuminance imaging capability

Imaging apparatus having a video memory function includes a video memory having a plurality of read ports and a capacity of storing images in two fields or more, wherein CCD storage sensitivity enhancement means is connected to a write port; a write control circuit for storing a single-field image in each memory area provided by dividing the storage space of the video memory into a plurality of sub-spaces; a plurality of read control sections for reading a single-field image stored in each memory area; and memory control means for reading an image from the video memory by a delay amount corresponding to the timing of a synchronization signal from the CCD storage sensitivity enhancement means. This configuration allows adjustment of the delay amount and prevents an image write address from passing by an image read address so that image data given CCD storage sensitivity enhancement is processed normally.

Imaging apparatus having video memory function

A video signal including illumination flicker component is integrated at each of unit areas (horizontal lines) in a frame (field) of the video signal. The integrated level at each of the unit areas at the frame and the integrated level at the corresponding unit area of an adjacent frame are averaged. Dividing is effected between results of the averaging and integrating every unit area. It is judged whether flicker exists in the video signal by frequency-analyzing results of the dividing result at the unit areas. The unit area may be plural adjacent lines where flickering are negligible. The averaging circuit may be circulation type of or FIR filter. Threshold level for judging the flicker is changed according to a shutter speed control signal. Flicker compensation may be executed by controlling shutter speed or the AGC according to flicker judging result. A still condition at a block in a frame may be detected from the integration result at plural frames. When the block is judged to be still, the flicker is judged. An ac line frequency detection is also disclosed to detect the frequency of the ac line from a video signal generated under illumination including flicker. An imaging circuit may be provided to generate the video signal therein.

ILLUMINATION FLICKER DETECTION APPARATUS, AN ILLUMINATION FLICKER COMPENSATION APPARATUS, AND AN AC LINE FREQUENCY DETECTION APPARATUS, METHODS OF DETECTING ILLUMINATION FLICKER, COMPENSATING ILLUMINATION FLICKER, AND MEASURING AC LINE FREQUENCY

A video signal processing circuit for processing a video signal including a noise is disclosed which comprises: an edge enhancement signal generation circuit for generating an edge enhancement signal from the video signal; a noise reduction circuit for reducing a level of the noise to generate a noise reduced video signal; and an adder for adding the edge enhancement signal to the noise reduction video signal to output a processed video signal. The apparatus may further comprise an input terminal for receiving the video signal, wherein the edge enhancement signal generation circuit and the noise reduction circuit coupled to the input terminal are in parallel. This apparatus may further comprise a first delay circuit for delaying the video signal by one horizontal line period to generate a 1-H delayed video signal and a second delay circuit responsive to the video signal for generating a 2-H delayed video signal, wherein the edge enhancement signal generation circuit generates the edge enhanced signal from the video signal, the 1-H delayed video signal, and the 2-H delayed video signal and the noise reduction circuit generates the noise reduced video signal from the video signal, the 1-H delayed video signal, and the 2-H-delayed video signal.

Video signal processing apparatus with noise reduction and edge

A video camera specifies as a photometric area any block of a field of image to be picked up and picks up a subject to be seen by optimizing the amount of light regardless of the position where a television camera is located. The video camera comprises a solid-state image pick-up element (CCD), a display device and devices for controlling the diaphragm of a lens. In operation, the image picked up by the solid-state image pick-up element is divided into plural blocks to be displayed. Any block of these plural blocks can be specified as a photometric area. The amount of light for the photometric area is calculated and the diaphragm of the lens is controlled so that the subject can be seen by optimizing amount of light.

Growing community of inventors

Yokohama, Japan

Makoto Sube