Oki Electric Industry Co., Ltd.

Makoto Shikata

Masahiro Akiyama

Yasushi Kawakami

Koutarou Tanaka

Koutaro Tanaka

A synthesized oscillation circuit that can relax a limitation of the maximum operational frequency. A mixer (MX), a bandpass filter (BPF), an amplitude limiting amplifier (LIM), a phase detector (PD), a low-pass filter (LPF), and a voltage-controlled oscillator (VCO) are serially connected between a signal input terminal (IN) and a signal output terminal (OUT). The signal output terminal (OUT) is connected the mixer (MX) and the phase detector (PD). The bandpass filter (BPF) has a filtering characteristic which blocks the sum frequency component of the frequency component of an input signal from the signal input terminal (IN) to the mixer (MX) and the frequency component of an output signal from the voltage-controlled oscillator (VCO) to the mixer (MX), but which passes the difference frequency component between them. The low-pass filter (LPF) has a filtering characteristic which blocks the sum frequency component of the frequency component of a signal from the voltage-controlled oscillator (VCO) to the phase detector (PD) and the frequency component of a signal from the voltage-controlled oscillator (VCO) to the phase detector (PD), but which passes the difference frequency signal between them.

Synthesized oscillation circuit

In a frequency-dividing circuit for producing an output having a frequency half that of its input, a pair of terminals of a latch circuit are connected to input terminals of a pair of amplify/delay means, and are also connected to receive through a pair of transistors, the outputs of the amplify/delay means. A single-phase input signal is input to the control electrodes of the transistors to turn on and off the transistors. When the transistors are turned from off to on, the output states of the amplify/delay means are transferred through the transistors to invert the latch circuit, and the states of complementary terminals of the latch circuits are in turn transferred through the amplify/delay means to invert the output states of the outputs of the amplify/delay means. When the transistors are turned from on to off, no change occurs in the states of the circuit. In this way, the states of the circuit are inverted each time the transistors are turned from off to on. A frequency-divided output can therefore be derived at one of the outputs of the first and second amplify/delay means. Either one or both of the first and second inverters may be replaced by a NAND gate or a NOR gate for permitting reset of the circuit.

Frequency-dividing circuit

A flip-flop circuit comprises a first transfer gate receiving input data and being conductive responsive to a clock signal, a second transfer gate receiving an inverted input data and being conductive responsive to said clock signal, a third transfer gate receiving said input data and being conductive responsive to an inverted clock signal, and a fourth transfer gate receiving said inverted input data and being conductive responsive to said inverted clock signal. First and second inverters are cross-coupled across output nodes of said first and second transfer gates to serve as a latch circuit. Third and fourth inverters are cross-coupled across output nodes of said third and fourth transfer gates to serve as a latch circuit. A selector selects either the outputs of the first and second transfer gates, or the outputs of the third and fourth transfer gates, as output data and inverted output data of the flip-flop circuit, in accordance with said clock and inverted clock signals.

Flip-flop circuit

A flip-flop circuit comprises two basic flip-flop circuits, four field effect transistors, and four amplifiers. The two basic flip-flop circuits respectively composed of a first and a second inverter circuits, and an output terminal of the first inverter circuit is connected to an input terminal of the second inverter circuit and an output terminal of the second inverter circuit is connected to the input terminal of the first inverter circuit. The field effect transistors have sources respectively connected to input terminals of the two basic flip-flop circuits, and gates to which clock pulses and inverse clock pulses are applied. The amplifiers respectively composed of an inverter circuit are connected to output terminals of the two basic flip-flop circuits.

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Tokyo, Japan

Makoto Shikata