Nec Corporation

Tok Corporation

Makoto Sekine

Ken Inoue

Daisuke Takahashi

Hirohito Watanabe

Tetsuya Homma

Hidenobu Miyamoto

Satoshi Kamiyama

Ichirou Honma

There is provided a hinge arm damper mechanism that reliably achieves a damper effect corresponding to a braking force of an elastic member. The hinge arm damper mechanism is configured to include a pinion gear, a pair of racks and, two sets of heavy load springs and, a pair of slide bars and, and a housing. The housing includes a box-shaped case and a plate-shaped cover. The case accommodates the pinion gear, the pair of racks and, the two sets of heavy load springs and, and the pair of slide bars and. A rotational torque applied to a hinge arm is transmitted to the racks and via a rotational motion of the pinion gear, and is converted into a linear motion of the racks and. The linear motion of the racks and is reliably braked by the respective springs and.

Hinge arm damper mechanism

A reverse input lock clutch has a fitting portion of a spring stopper rotatably fitted in a cylindrical dent formed by being surrounded by an inner diameter portion on an end surface of an output member on a side opposite to a fixed member. A locking portion rotates with the fitting portion while having one end of a first elastic member locked by a holder groove. Adjustment of the rotation position of the lock portion with respect to the output member is made by rotating the fitting portion within a range of a groove length of an adjustment groove with respect to the output member and anchoring an adjustment pin at a desired rotation position to the adjustment pin fixing portion so as to fix the fitting portion on the output member.

Reverse input lock clutch

A method for fabricating a CMOS transistor having a salicide structure is disclosed. A naturally formed oxide film covering surfaces of polycrystalline silicon film patterns, a P-type diffusion layer and an N-type diffusion layer is removed. Then, by introducing at least a titanium tetrachloride gas and a hydrogen gas into an electron cyclotron resonance plasma excited chemical vapor deposition system using microwaves (or into a plasma excited chemical vapor deposition system using helicon waves), titanium/silicide films are selectively formed on surfaces of the polycrystalline silicon film patterns and the P-type diffusion layer and the N-type diffusion layer. The crystal structure of the titanium/silicide films is of a C54 structure. During the formation of the titanium/silicide film, it is possible to suppress the occurrence of bridging and condensation phenomena.

Method for fabricating CMOS transistor with self-aligned silicide

A polysilicon film is deposited on a semiconductor substrate. A PSG film that can be removed from a material that composes field oxide films and sidewalls of a side surface portion of a gate electrode with a satisfactory selective ratio is deposited on the resultant semiconductor substrate. After the deposited films are processed as a gate electrode, the sidewalls are formed on the side surface portion of the gate electrode. Thereafter, the PSG film is selectively removed and the front surface of the polysilicon film, which composes the gate electrode, is exposed. Tungsten films are deposited on the front surfaces of the polysilicon film and source and drain region formed on the semiconductor substrate. After the SiON film is formed on the resultant semiconductor substrate, contact holes and then contacts are formed on the SiON film.

Semiconductor apparatus and fabrication method thereof

The present invention provides a novel method for forming multilevel interconnections in a semiconductor device. A silicon oxide film is formed on a semiconductor substrate. A first photo-resist film pattern is formed on the first silicon oxide film. The surface of the silicon oxide film covered with the photo-resist film pattern is exposed to a super-saturated hydrosilicofluoric acid solution to selectively deposit a first fluoro-containing silicon oxide film on the silicon oxide film by use of the first photo-resist film pattern as a mask. The first photo-resist film pattern is removed, thereby resulting in first grooves in the fluoro-containing silicon oxide film. First interconnections are formed within the first grooves. An inter-layer insulator is formed on an entire surface of the device and then subjected to a dry etching and a photolithography to form via holes in the inter-layer insulator. Conductive films are selectively formed in the via holes. A second photo-resist film pattern is selectively formed to cover the conductive films within the via holes. The entire surface of the device covered with the second photo-resist film pattern is exposed to a super-saturated hydrosilicofluoric acid solution to selectively deposit a second fluoro-containing silicon oxide film on the inter-layer insulator by use of the second photo-resist film pattern as a mask. The second photo-resist film pattern is removed, thereby resulting in second grooves in the second fluoro-containing silicon oxide film. Second interconnections are formed within the second grooves.

Method for forming multilevel interconnections in a semiconductor device

The method of fabricating a semiconductor device, includes the steps of (a) forming gate oxides on regions separated by device isolation regions, (b) depositing an amorphous silicon or a polysilicon film, (c) depositing a removable space-forming film over the silicon film, (d) patterning the space-forming film and the silicon film into the same shape to form a gate electrode comprising the thus patterned space-forming film and silicon film, (e) depositing a silicon nitride film, (f) etching the silicon nitride film to form a first sidewall around a sidewall of the gate electrode, (g) depositing a silicon oxide film, (h) etching the silicon oxide film to form a second sidewall around and onto the first sidewall, (i) etching the space-forming film with hydrofluoric anhydride for removal so that the silicon film is exposed and the first sidewall remains unremoved, (j) forming source/drain regions, and (k) selectively depositing a refractory metal or metal silicide film on the silicon film and the source/drain regions. The method makes it easy to cause the first sidewall to have higher height than the amorphous or polysilicon film to thereby form low-resistance gate electrode and diffusion layers, resulting in that the gate electrode is not short-circuited with the diffusion layers.

Method of fabricating semiconductor device having low-resistance gate

A semiconductor device has a capacitive element with excellent leak current characteristics which has a tungsten film with a roughened surface for increasing the surface of a lower electrode. A capacitive element for use in a VLSI memory circuit such as a DRAM or the like is fabricated by forming a thin, roughened tungsten film selectively on a surface of a lower electrode of polysilicon by chemical vapor-phase growth and forming a capacitive insulating film on the surface of the lower electrode of polysilicon, densifying the capacitive insulating film, and forming an upper electrode of a metal element.

Growing community of inventors

Tokyo, Japan

Makoto Sekine