Hitachi, Ltd.

Renesas Technology Corp.

Renesas Electronics Corporation

Makoto Saen

Kenichi Osada

Tomonori Sekiguchi

Kiyoto Ito

Yusuke Kanno

Motoyasu Terao

Hitoshi Kume

Satoru Hanzawa

Tetsuya Yamada

Itaru Nonomura

Shigenobu Komatsu

Satoshi Misaka

Masanao Yamaoka

Futoshi Furuta

Masafumi Onouchi

Yuki Kuroda

Keisuke Toyama

Takeshi Sakata

Hiroshi Ueda

Kei Suzuki

Yasuhisa Shimazaki

Hiroyuki Sasaki

Yoshimitsu Yanagawa

Shigeru Oho

Takanobu Tsunoda

Tomomi Takahashi

Eiji Yamamoto

Jun Matsushima

Kazuo Otsuga

Tomoyoshi Ujii

Yuri Ikeda

Masashi Ohkawa

Yoshikazu Aoto

In a device including a programmable circuit, the programmable circuit is connected to a non-volatile memory in which configuration information is stored, and another memory having a faster reading speed than the non-volatile memory, and the programmable circuit includes a configuration memory control circuit, and a signal line group for performing reading with respect to the other memory such as a volatile memory and an embedded memory from the non-volatile memory by the configuration memory control circuit, and copies a part of circuit configuration information which is required to be subjected to fast restoration from failure into the other memory.

Programmable circuit device and configuration information restoration method

A manipulator device has an arm portion and a hand portion The hand portion includes one or more finger portions that manipulate a target object. Each finger portion includes a slip sensor and multiple contact sensors, with at least one contact sensor at a position proximate to the slip sensor and at least another contact sensor at a position remote from the slip sensor. When the contact sensors at the positions remote from the slip sensor detect contact of the target object and the contact sensors arranged at the positions proximate to the slip sensors do not detect contact, a position of the finger portion is moved by a distance corresponding to the distance between the contact sensors detecting contact of the target object and the contact sensors arranged at the positions proximate to the slip such that a detecting position of the slip sensor is coincident with a position of the target object.

Manipulator device

It has been difficult to carry out a test and an analysis with respect to combinational logic circuits mounted across plural chips, and therefore, there is provided a flip-flop () by use of which either of a scan chain within a semiconductor chip (LSI_B), and a scan chain across plural semiconductor chips (LSI_A and LSI_B) can be made up.

Semiconductor device, and test method for same

The need for mediation operation is eliminated by adoption of a connection topology in which a circuit for executing one transmission (TRT), and a circuit for executing a plurality of receptions (TRR, TRR, TRR) are connected to one penetration-electrode group (for example, TSVGL). In order to implement the connection topology even in the case of piling up a plurality of LSIs one after another, in particular, a programmable memory element for designating respective penetration-electrode ports for use in transmit, or for us in receive, and address allocation of the respective penetration-electrode ports is mounted in stacked LSIs.

Semiconductor apparatus

A highly reliable large capacity phase change memory module is realized. A semiconductor device according to the present invention includes a memory array having a structure in which a storage layer using a chalcogenide material and a memory cell constituted of a diode are stacked, and an initialization condition and a rewriting condition are changed in accordance with the layer where a selected memory cell is located. A current mirror circuit is selected in accordance with an operation, and at the same time, the initialization condition and the rewriting condition (here, reset condition) are changed in accordance with the operation by a control mechanism of the reset current in a voltage selection circuit and a current mirror circuit.

Method of manufacturing non-volatile memory module

There is a need to ensure operation performance of a circuit region under DVFS control at low costs and highly precisely while a power-supply voltage change is made to the region. A first circuit (FVA) uses a first power-supply voltage (VDDA) for operation. A second circuit (NFVA) uses a second power-supply voltage (VDDB) for operation. A clock delay may be adjusted between paths for transmitting a clock to these circuits. When VDDA equals VDDB, a clock is distributed to FVA through a path that does not contain a delay device for phase adjustment. When the power-supply voltage for the FVA region is reduced, a clock is distributed to the FVA region based on a phase equivalent to one or two cycles of the clock displaced. Synchronization control is provided to synchronize clocks (CKAF and CKBF) and ensures operation so that a phase of two clocks to be compared fits in a range of design values while the power-supply voltage for the first circuit is changed.

Semiconductor integrated circuit and control method for clock signal synchronization

A semiconductor integrated circuit device capable of achieving improvement of I/O processing performance, reduction of power consumption, and reduction of cost is provided. Provided is a semiconductor integrated circuit device including, for example, a plurality of semiconductor chips stacked and mounted, the chips having data transceiving terminals bus-connected via through-vias, and data transmission and reception are performed via the bus with using the lowest source voltage among source voltages of internal core circuits of the chips. In accordance with that, a source voltage terminal of an n-th chip to be at the lowest source voltage is connected with source voltage terminals for data transceiving circuits of the other semiconductor chips via through-vias.

Semiconductor integrated circuit device

In a test method of stacked LSIs connected by Through Silicon Vias, it is difficult to perform a failure diagnosis by using a conventional device test method to only one side of a silicon wafer, there is a possibility of yield degradation at a stacking time of LSIs, and a plurality of LSIs is connected to one Through Silicon Via so that it is necessary to select and remedy a defective Through Silicon Via taking into account all the device states. These problems cannot be solved by conventional test methods. Therefore, for a device test of a Through Silicon Via through a plurality of chips, a circuit that generates a time-series test pattern having both 0 and 1 values for a delay fault test is added to a circuit portion that transmits data to a Through Silicon Via in the stacked LSIs, and a circuit that receives the test pattern and compares the pattern received with a fixed pattern for a match to detect a defect of a Through Silicon Via is added to a circuit portion that receives data from a Through Silicon Via in the stacked LSIs.

Semiconductor device

In a through-via-hole path of semiconductor chips stacked in N stages, repeater circuits are provided in the respective semiconductor chips. For example, a signal transmitted from an output buffer circuit of the semiconductor chip is transmitted to an input buffer circuit of the semiconductor chip via the repeater circuits of the respective semiconductor chips. The respective repeater circuits can isolate impedances on input sides and output sides, and therefore, a deterioration of a waveform quality accompanied by a parasitic capacitance parasitic on the through-via-hole path of the respective semiconductor chips can be reduced and a high speed signal can be transmitted.

Semiconductor integrated circuit device comprising a plurality of semiconductor chips mounted to stack for transmitting a signal between the semiconductor chips

In a vehicle electronic system including a plurality of LSI boards, LSIS which cannot control a user interface such as image or audio directly issue a command for notifying a vehicle occupant of its own information via networks and an information control LSI receives the request to output a message. A mechanism for setting priority of processings regarding LSI status information notification to be lower than that of an apparatus control processing is provided in each of LSIs and networks so that real-time property of the apparatus control processing is maintained. In order to reduce network load regarding the LSI status information notification, a message content itself is stored in a memory in a vehicle information processing unit previously so that only an ID for identifying the message content is transmitted.

Vehicle electronic system and vehicle

Traffic between logic LSIs and memory is increasing year by year and there is demand for increase of capacity of communication between them and reduction of power consumption in the communication. Communication distances between LSIs can be reduced by stacking the LSIs. However, in a simple stack of logic LSIs and memory LSIs, it is difficult to ensure heat dissipation to cope with increasing heat densities and ensure transmission characteristics for fast communication with the outside of the stacked package. Also required is a connection topology that improves the performance of communication among the stacked LSIs while ensuring the versatility of the LSIs. An external-communication LSI, a memory LSI, and a logic LSI are stacked in this order in a semiconductor package and are interconnected by through silicon vias. Output terminals of multiple stacked LSIs are connected to an input terminal of a through silicon via of the stacked memory LSI and input terminals of multiple stacked LSIs are connected to an output terminal of a through silicon via of the stacked memory LSI, thereby directly connecting both of the external-communication LSI and the logic LSI to a wiring line of the memory LSI.

A semiconductor device including a pair of stacked semiconductor ICs capable of communicating with each other by wireless. Each IC has: a transmitter circuit operable to send, by wireless, transmit data together with a clock signal deciding a transmission timing, and arranged so that the wireless transmission timing is adjustable; a receiver circuit operable to receive data in synchronization with a clock signal received by wireless, and arranged so that its wireless reception timing is adjustable; and a control circuit operable to perform timing adjustments of the transmitter and receiver circuits based on a result of authentication of data returned by the other IC in response to data transmitted through the transmitter circuit, and received by the receiver circuit. This arrangement for near field communication between stacked semiconductor ICs enables: reduction of the scale of a circuit for communication timing adjustment; and highly accurate adjustment of the communication timing.

Growing community of inventors

Kodaira, Japan

Makoto Saen