Fujitsu Corporation

Nippon Telegraph and Telephone Corporation

Makoto Okazaki

Yuji Shibata

Hisamitsu Tanihira

Koji Eto

Masao Asai

Yoshiaki Wakimura

Katsuyuki Okada

A dual system has system buses that are connected to each other through bus interchange apparatuses and a cross bus to transfer information between the system buses. Each of the bus interchange apparatuses has a first bus controller ( ) having a reception controller ( ) and a transmission controller ( ) that are connected to one ( ) of the system buses, a second bus controller ( ) having a reception controller ( ) and a transmission controller ( ) that are connected to the cross bus ( ), buffers ( ) for relaying information between the first and second bus controllers ( ), and a register ( ) directly accessible from the first and second bus controllers ( ) to write fault information thereto.

Bus interchange apparatus and dual system for accessing a fault information register without regard to buffer conditions

A bus interface system has a bus interface, a common memory, a local bus, and a memory controller for use in a memory control. The memory controller has a buffer and is connected to the local bus. The bus interface has a burst disassembling control circuit which disassembles burst transfer data into one or a plurality of block transfers and one or a plurality of one-word transfers, which are supplied to the memory controller so that when the bus interface receives all requested data received from the common memory during a read access, the bus interface adds information on a destination device, connected to a system bus, to all the requested data and sends all the requested data with that information to the destination device via the system bus.

Bus interface structure and system for controlling the bus interface

A bus arbiter permits an answer transfer request to utilize a system bus with higher priority than a command transfer request, thereby increasing the processing efficiency of CPU boards. A multi-processor system utilize the system bus with a time split transfer system in which the data width of a unit is inserted into a command and an answer transmitted and received between processors and transmitted as bus width information, thus making it possible to interconnect a unit, which processes data of an arbitrary data width, to the system bus. Local memories of a plurality of units connected to the system bus can be accessed via a bus interface of an input and output unit.

Bus control system in a multi-processor system

A parity inversion test system includes an interface part having an input side coupled to a N-bit data line and an output side coupled to a M-bit data line, where N&lt;M, an output coupling part for coupling at least a part of a data output from the output side of the interface part to the data output from the output side of the interface part in a test mode so as to output a M-bit data, a parity generating part for generating a parity data with respect to the M-bit data output to the M-bit data line via the output coupling part based on the M-bit data, and a parity inversion bit specifying part for specifying arbitrary bits of the M-bit data output to the M-bit data line which are to be inverted when generating the parity data in the parity generating part.

Parity inversion test system

Bus interface circuit for controlling data transfer

An isolated speech word recognizer for recognizing an input pattern as one of a plurality of known patterns, comprising a similarity information storing unit for storing similarity information representing the degree of significance of a feature in each of the known patterns for recognizing thereof, and a most similar pattern determining unit for determining one of the plurality of known patterns as the most similar pattern to the input pattern by the use of the similarity information, whereby the recognition performance is improved.

Speech word recognizing apparatus using information indicative of the

An isolated speech word is extracted from an input speech signal. First, the speech signal is divided into a high frequency band signal and a low frequency band signal. Next, the power levels of each of the high and low frequency band signals are independently compared with respective threshold levels. Finally, the front and the end of the speech word are detected from these independent comparisons.

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Kawasaki, Japan

Makoto Okazaki