Nec Corporation

Makoto Ohtsuka

Yuzo Shimada

Naoji Senba

Hiroki Hihara

Hiroaki Miyoshi

Hideki Kusamitu

Katsumasa Hashimoto

Ikusi Morizaki

Yasuhiko Mizushima

A three-dimensional memory module includes a plurality of semiconductor device units, every adjacent two of which are stack-connected via through-holes by a bump connecting method. Each of the plurality of semiconductor device units includes a carrier having a circuit pattern and the through-holes connected to the circuit pattern. The semiconductor device unit also includes at least one semiconductor memory chip mounted on the carrier such that the semiconductor memory chip is connected to the circuit pattern, and at least one chip select semiconductor chip mounted on the carrier to be connected to the circuit pattern such that the chip select semiconductor chip can select the semiconductor memory chip.

Stacked carrier three-dimensional memory module and semiconductor device

In each module (11) of three or more central processor modules of a fault tolerant computer system, a detector (45) receives a comparator output signal and like comparator output signals from two adjacent modules and produces a detector output signal which confirms absence and presence of a fault in one of the above-mentioned each module. When the fault is confirmed, a controller or processor (49) isolates the module under consideration from the system by inhibiting delivery of a controlled output signal to a bus (31) and by connecting, with the module in question bypassed, switching units (53(1), 53(2)) of the adjacent modules. Preferably, one of the modules of the system is used as a master module of ordinarily delivering the controlled output signal to the bus with others used as checker modules of ordinarily inhibiting the delivery. When a fault appears in the master module, its controller delivers a module operation switching signal to the controllers of the checker modules to thereby substitute one of the checker modules for the master module subjected to the fault.

Fault tolerant computer system comprising a fault detector in each

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Tokyo, Japan

Makoto Ohtsuka