Hitachi, Ltd.

Hitachi Denshi Kabushiki Kaisha

Oki Electric Industry Co., Ltd.

Nippon Hoso' Kyokai

Hitachi Denshi Kabushiki

Makoto Ohnishi

Hiroshi Kuwahara

Shigeki Nakamura

Eiichi Amada

Naoya Kobayashi

Yoshiro Kokuryo

Yasufumi Takahashi

Masaaki Ohta

Masahiro Kageyama

Hiroshi Yoshigi

Hirotoshi Shirasu

Kazuo Ishikura

Yoshiaki Asakawa

Yukinari Fujiwara

Masaru Adachi

Narimichi Maeda

Takahiko Fukinuki

Masahiro Koya

Kazuhisa Hayeiwa

Fumihito Tomaru

Yoshihiko Nasu

Norihiro Suzuki

Yasuko Shinata

Toshiaki Nario

Ikuzi Fuzitani

Hirotake Wakai

A USB system is capable of connecting, based on the function of constructing and connecting a virtual port by a virtual port constructing functional unit, a number of devices exceeding a prescribed number of tiers having a hub device in a connection topology of a host device&#x2014;hub devices&#x2014;a device of the USB system. When the host device addresses a device on its downstream side, the hub device acts as if it is a specified device by a proxy response functional unit including the hub device, and instantaneously performs a proxy response depending upon the situation that, for example, the device on its downstream side is not ready. This causes no problem associated with the turn-around time of the USB bus even if the prescribed number of tiers is exceeded.

Bus communication system by unrestrained connection and a communication control method therefor

A digital demodulator which demodulates an analog signal obtained through a quadrature amplitude modulation to produce a digital demodulated signal includes a converter to convert the analog signal into a digital signal and a signal processor to quadrature-demodulating the digital signal from the converter. Assuming that the analog signal has a carrier frequency of f.sub.IF and the signal conversion is accomplished with the sampling frequency fs, the demodulator is set to satisfy fs=4.multidot.f.sub.IF /(2n+1), where n denotes a positive integer. The signal processing section conducts the quadrature demodulation according to a quadrature local oscillation signal having a frequency fc satisfying fc=fs/4.

Digital modulator having a digital filter including low-speed circuit

An FDMA (Frequency-Division Multiple Access) transmitter-receiver for use in an FDMA communication system which is capable of changing a bandwidth of a channel as required. The FDMA transmitter-receiver includes: a plurality of trans-demultiplexers which are different in the number of channel multiplexings from each other and each of which serves to convert the received FDMA signal into a TDMA signal; a communication signal demultiplexing/multiplexing circuit for subjecting the output communication channel signals from the trans-demultiplexers to demultiplex and channel-reassignable multiplex them; a plurality of trans-multiplexers which are provided in correspondence to the plurality of trans-demultiplexers and each of which serves to convert the output channel signal after demultiplexing and remultiplexing from the associated communication signal demultiplexing/multiplexing circuit into an FDMA signal; an adder for adding the FDMA signals outputted from the trans-multiplexers; and a transmission circuit connected to an output of the adder for transmitting therefrom the signal which has been obtained by adding the FDMA signals. The bandwidth per channel of each of the trans-demultiplexers and the trans-multiplexers is different in correspondence to the number of channel multiplexing.

Transmission/reception method based on frequency division multiple

The FM stereo broadcasting apparatus has a sampling frequency converter for receiving a digital input signal having an L (left audio)-signal and an R (right audio)-signal and for converting the digital input signal so that its sampling frequency is equal to either a frequency of a subcarrier of a composite audio signal or a first sampling frequency of a first sampling signal for the operation of a composite audio signal generator, a sampling signal generator for generating the first sampling signal for the operation of the composite audio signal generator having the first sampling frequency which is equal to 2.sup.N times (N is an integer of 1 or above) as high as the frequency of the subcarrier, a composite audio signal generator which is operated by the first sampling signal and which generates the composite audio signal on the basis of a pilot signal and the L-signal and R-signal of the input signal from the first frequency converter, and a frequency modulator for modulating the frequency of a carrier signal by the composite audio signal from the composite audio signal generator so as to produce a frequency-modulated signal.

FM stereo broadcasting apparatus and method

There is provided a maximum likelihood decoding method, and an apparatus, capable of correcting burst errors caused by abrupt lowering of the signal amplitude. The soft decision maximum likelihood decoding method is a maximum likelihood decoding method for conducting maximum likelihood decoding on a received train resulting from addition of an error train to a transmission code train, which has been obtained by coding an information train by using convolutional codes on a transmission side. The soft decision maximum likelihood decoding method includes the step of making corrections by multiplying the soft decision likelihood metric having a multi-valued level, which has been obtained by soft decision likelihood metric from the received train, by weighting coefficients depending upon an instantaneous amplitude of the received signal, and the step of conducting maximum likelihood decoding by using corrected soft decision likelihood metric values. Thereby, it becomes possible to enhance the error correcting capability of error correcting apparatuses used in mobile radio communication or the like with severe fading. As a result, communication reliability is increased.

Soft decision maximum likelihood decoding method with adaptive metric

In a complex modulation/demodulation method and system, the data frequency f.sub.C1 of data signals I and Q inputted to a constellation mapping circuit is converted by a digital interpolation circuit into a sampling frequency f.sub.C2 equal to f.sub.S /N, where f.sub.S is an operation sampling frequency and N is selected such that the signal maximum frequency of the data signals I and Q becomes lower than f.sub.C2 /2. The interpolated data signals I and Q are respectively inputted to real and imaginary input terminals of a complex coefficient band pass filter to extract a real signal output. An output signal of the complex coefficient band pass filter is converted by a DA converter into an analog signal from which desired frequency components are extracted by an analog band pass filter, thereby performing a quadrature modulation.

Modulation/demodulation method and system for realizing quadrature

A scanning line interpolation circuit for reproducing scanning lines not transmitted through interpolation on the basis of a main scanning line signal and an auxiliary signal both transmitted, wherein an interpolated scanning line signal is generated on the basis of the main scanning line signal and auxiliary signal with respect to a frequency band used to transmit the auxiliary signal and an interpolated scanning line is generated in response to picture motion on the basis of only the main scanning line signal with respect to a frequency band used not to transmit the auxiliary signal.

Scanning line interpolation circuit

A simplified carrier phase control apparatus used in a modem for demodulating a quadrature amplitude modulated data signal, to correct phase jitters of a carrier signal due to a 50 Hz or a 60 Hz frequency of the commercial power supply, and its harmonic wave frequency components. The carrier phase control apparatus has a predictive filter for predicting a carrier phase jitter, the predictive filter composed of band-pass filters with center frequencies of 50 Hz and 60 Hz, and a circuit where the output signals of the band-pass filters are multiplied by the coefficients and added linearly.

Carrier phase controller for a receiver of phase modulated signals

A maximum likelihood decoder for decoding a code from a signal transmitted through quadrature amplitude modulation of a code including a convolutional code can decode at high speed and high accuracy with a simple hardware configuration. In the maximum likelihood decoding of the convolutional code, the metric processing is not carried out for all of the possible paths and states but a smaller number of path(s) (metric(s)) and state(s) (metric(s)) are selected in a descending order to determine survival paths.

Maximum likelihood decoder

A digital demodulator for separating and demodulating quadrature modulated signals to produce the inphase components and quadrature components of a baseband through simple digital processing. This digital demodulator is constructed by an A/D converter for sampling received modulated signal so as to be converted into digital signals, means for distributing every other sample signal of the sample signals from said A/D converter into two trains of the sample signals, means for inverting the polarity of every other signal of the one signal train so as to provide the inphase components of the baseband, and means for delaying the other signal sequence by one sampling period and thereafter inverting the polarity of every other signal of the delayed signals so as to provide the quadrature components of the baseband.

Digitally processed demodulator for quadrature modulated signals

A quadrature phase modulator constructed by use of a simple digital circuit. Digital signals of sample data obtained by sampling outputs from a roll-off filter with a frequency four times a modulated carrier frequency are stored in an ROM, the outputs corresponding to all combinations of a plurality of successive bits of input data; the plurality of bits are set as an address, and a signal of an in-phase channel and a signal of a quadrature phase channel is alternately read from the ROM with a frequency equal to half the sampling frequency, then the obtained serial signals are subjected to a digital-to-analog conversion to obtain a quadrature phase modulated signal.

Digital modulation apparatus

A recursive-type digital filter comprising a calculation circuit. The calculation circuit is arranged to multiply an input signal including at least m-bit signal x.sub.n inputted at a predetermined sampling period and an output signal y.sub.n-k fed back to the input of the calculation circuit in accordance with the input signal x.sub.n after being subjected to a delay of k sampling periods by a.sub.k and b.sub.k coefficients corresponding to the filter characteristics, respectively, and then the products are added thereby to produce data y.sub.n of (m+l) bits satisfying, ##EQU1## and serially deliver the upper m-bit data of the data y.sub.n as an output signal corresponding to the input signal x.sub.n. The filter further comprises a delay circuit for feeding back to the input of the calculation circuit a part of the round off data including the upper (m+1)th bit of the data y.sub.n so that the b.sub.k coefficient is multiplied by the fedback data of the upper (m+1)th bit and the product is added to the data y.sub.n, thereby to produce an output signal with reduced round off noise.

Recursive-type digital filter with reduced round-off noise

A recursive type digital filter receiving a digital input signal x(n) having a plurality of bits and delivering a ditial output signal y(n) satisfying the following equation, ##EQU1## where n indicates a natural number, M and N orders of time lag in the signal transference, a.sub.k and b.sub.k coefficients defined by a filter characteristic, a.sub.M and b.sub.N b being coefficients which are not equal to zero, comprises an output control circuit for delivering a digital signal indicating a positive or negative limit value in place of the digital output signal y(n) when the amplitude of the signal y(n) exceeds an allowable value. In combination with this output control circuit, the filter also utilizes a feedback signal for calculation purposes which feedback signal has its amplitude reduced from that of y(n) by a predetermined ratio. Further, an arrangement is provided for clearing registers of filter when necessary to prevent overflow oscillation.

Recursive type digital filter

A digital adder comprises at least two, first and second 1-bit adders; first and second carry circuits which store therein output signals of carry output terminals of said first and second adders and apply them to carry input terminals of said first and second adders, respectively, in response to a predetermined clock signal; first input means for applying each pair of a plurality of pairs of data to be added up and each consisting of a predetermined number of bits, to said first adder in 1-bit sequence from least significant bits of said each pair of data in response to said clock signal; second input means for applying the data to be added to the carry signal delivered from said first adder by the addition of most significant bits of said each pair of data, to said second adder in 1-bit sequence from the least significant bits in response to said clock signal and upon termination of the application of said pair of data to said first adder; a first gate circuit which inhibits the carry signal delivered from said first adder by the addition of the most significant bits of said each pair of data, from being applied to said first carry circuit and applies said carry signal to said second carry circuit; and means for combining outputs of said first and second adders so as to attach the output of said second adder onto a more significant bit side of the output of said first adder and for delivering the combined output as one data.

Digital adder circuit with a plurality of 1-bit adders and improved

In a time-division-multiplexed exchanger having digital filters disposed in a channel system, a level adjuster wherein data for setting line losses corresponding to respective combinations of interconnections of a plurality of lines received at outgoing and incoming line terminals of the time-division-multiplexed exchanger are stored by storage means, and coefficients of the digital filters are controlled on the basis of the data at exchange operations, whereby the level adjustment is made.

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Tokyo, Japan

Makoto Ohnishi