Mitsubishi Denki Kabushiki Kaisha

Mitsubishi Electric Corporation

Makoto Ohi

Natsuo Ajika

Hideaki Arima

Atsushi Hachisuka

Tomonori Okudaira

Yuichi Kunori

Hiroshi Onoda

Atsushi Fukumoto

Yasushi Matsui

Takeshi Nakayama

Shinichi Kobayashi

Kaoru Motonami

Yasushi Terada

Yoshikazu Miyawaki

Tomoshi Futatsuya

Hidekazu Arita

Vehicle-mounted equipment includes a storage unitfor storing data for a plurality of destinations, a vehicle-mounted network connecting unitfor receiving destination data indicating a destination via a vehicle-mounted network, a destination determining unitfor determining the destination on the basis of destination data received by the vehicle-mounted network connecting unit, and a data deleting unitfor deleting data other than data for the destination determined by the destination determining unit from the storage unit.

Vehicle-mounted equipment

A route search system includes a map data storing meansstoring a roadmap data containing, as the attribute of a road, whether the road is a road located within a flat-rate pay area where a fixed fare is charged on a mobile unit regardless of the number of times the mobile unit enters the area if the entries are made within a fixed time period; a flat-rate pay area transit recording meanswhen the current position detected by a position detecting meanscomes to a road in the flat-rate pay area represented by the attribute of the roadmap data stored in the map data storing means, storing that the mobile unit has transited the flat-rate pay area; an input meansinputting whether to permit transit across the flat-rate pay area; and a route calculating meanswhen it is inputted by the input means that the transit thereof is not permitted, if the flat-rate pay area transit recording means stores that the mobile unit has transited the flat-rate pay area, calculating the optimum route to the destination within routes also containing roads located within the flat-rate pay area on the basis of the roadmap data stored in the map data storing means.

Route search system

A navigation apparatus includes a map information updating means () for updating map information on a basis of map update information, a mounting detecting means () for detecting whether a storage medium is mounted to a storage medium driving means, a map information ID comparison means () for comparing a map information ID attached to the map information with a map information ID attached to the map update information to judge whether they match each other, a map information selection control means () for, when the storage medium is mounted to the storage medium driving means and the map information IDs match each other, selecting all of the map information, and selecting a part of the map information otherwise, a navigation information calculating means () for creating navigation information on the basis of the selected map information, and a navigation information output means () for outputting the created navigation information.

Navigation apparatus

In erasing, electrons are simultaneously injected into floating gates from sources of a plurality of memory cells. Thus, the threshold voltages of the plurality of memory cells are increased. In programming, electrons are emitted from a floating gate of a selected memory cell to a drain. Thus, the threshold voltage of the selected memory cell is reduced.

Electrically programmable and erasable nonvolatile semiconductor memory

A capacitor includes a polycrystalline silicon layer 1 as a lower electrode layer, a dielectric layer 112, and a polycrystalline silicon layer 113 as an upper electrode layer. The dielectric layer 112 is formed by an oxynitride film 2, a silicon nitride film 3 and a top oxide film 4. A film thickness t.sub.3 of the top oxide film 4 is controlled to be less than 20 .ANG.. Capacitance of the capacitor can be increased while improving the duration of life of the dielectric layer, resulting in a highly reliable capacitor.

Method of manufacturing a semiconductor device having a capacitor

Disclosed is a semiconductor memory device in which defects in crystal in a junction region between a capacitor and a source/drain region, and a short channel effect of a transistor can be effectively reduced. The semiconductor memory device includes, on the side of a gate electrode at which the capacitor is connected, a sidewall formed to have a width larger than that of a sidewall on the side of a bit line, and a source/drain region to which the capacitor is connected and which is formed to have a diffusion depth larger than that of the opposite source/drain region. Therefore, the source/drain region effectively prevents defects in crystal from being produced in the junction region between the capacitor and the source/drain region connected to the capacitor and the sidewall effectively reduces the short channel effect.

Field effect transistor having impurity regions of different depths and

In a semiconductor memory device according to the present invention, a conductive layer is formed on a field oxide film in a boundary region on the main surface of a semiconductor substrate. A floating gate electrode, an interlayer insulating film, and a control gate electrode are formed on the semiconductor substrate in a memory cell array region with a gate insulating film interposed therebetween. A gate electrode is formed in a peripheral circuit region with the gate insulating film interposed therebetween. An interlayer insulating film is formed on the conductive layer, the gate electrode, and the control gate electrode. A contact hole is formed at a predetermined position of the interlayer insulating film. An interconnection layer is selectively formed on the interlayer insulating film including the inner surface of the contact hole. According to the present invention, it is possible to prevent formation of a concave portion on the surface of the field oxide film in the boundary region. It is also possible to protect the memory cell array region from an external noise by forming the conductive layer on the field oxide film in the boundary region and by fixing the potential of the conductive layer.

Method of making memory cells with peripheral transistors

Semiconductor device having capacitor and manufacturing method therefor

Semiconductor memory device and method of manufacturing the same

A method of making a semiconductor device including a plurality of gate electrodes (6a, 6b, 6c, 6d) arranged on the surface of a semiconductor substrate (1) with insulating layers (5, 8) covering the top and the side walls of the gate electrodes. The spaces between the opposing side walls of adjacent gate electrodes on the surface of the element isolation region (2) are smaller than twice the thickness of the thinnest insulating layer (8) among the insulating layers of the side walls of the gate electrodes on the surface of the active regions. The space (14) between the gate electrodes on the element isolation region is filled with the insulating isolation layer (8) so that unevenness in the underlying portion on the element isolation region on which the conductive interconnection layer (10) to be formed is reduced, preventing thinning of the conductive interconnection layer and disconnection due to excessive etching of a resist film in patterning the conductive interconnection layer.

Method of making a semiconductor integrated device having gate sidewall

The width of a charge storage electrode and a control electrode in the column direction is set to be wider above an element isolation region than that above a channel region. Therefore, the capacitance between the control electrode and the charge storage electrode can be increased to improve the coupling ratio in a nonvolatile semiconductor memory device. Also, a first interconnection layer is equal in height above the control electrode and above the channel region, so that patterning of the first interconnection layer can be carried out easily and precisely.

Nonvolatile semiconductor device and a method of manufacturing thereof

A semiconductor device includes a plurality of gate electrodes (6a, 6b, 6c, 6d) arranged on the surface of a semiconductor substrate (1) with insulating layers (5, 8) covering the top and the side walls of the gate electrodes. The spaces between the opposing side walls of adjacent gate electrodes on the surface of the element isolation region (2) re smaller than twice the thickness of the thinnest insulating layer (8) among the insulating layers of the side walls of the gate electrodes on the surface of the active regions. The space (14) between the gate electrodes on the element isolation region is filled with the insulating isolation layer (8) so that unevenness in the underlying portion on the element isolation region on which the conductive interconnection layer (10) to be formed is reduced, preventing thinning of the conductive interconnection layer and disconnection due to excessive etching of a resin film in patterning the conductive interconnection layer.

Growing community of inventors

Hyogo, Japan

Makoto Ohi