Renesas Electronics Corporation

Nec Corporation

Mitsubishi Heavy Industries Limited

Makoto Nonaka

Naoaki Fujiwara

Yohei Nakajima

Tadashi Yazaki

Toshiaki Terayama

Tooru Nishikawa

To provide a semiconductor device with a digital-controlled DC-DC converter capable of stable feedback operation while minimizing area, the semiconductor device includes a DC-DC converter whose characteristic is determined by the control parameter, a flash memory and a processor that controls the flash memory, both of which operate at a power supply based on the output of the DC-DC converter. The control parameter is stored in the flash memory, and the control parameter is read out from the flash memory and set in the DC-DC converter by the processor while the DC-DC converter is operating.

Semiconductor device, system, and control method

An assembled mandrel for forming a hollow structure having a shape similar to that of the assembled mandrel, by layering a prepreg on the surface of the longitudinally oriented assembled mandrel, covering the same with a vacuum bag, heating while creating a vacuum inside the vacuum bag, and heat-curing the prepreg while pressing the same into the assembled mandrel, the assembled mandrel being characterized by being equipped with: two outer mandrel members (first mandrel members) extending in the longitudinal direction; a center mandrel member (second mandrel member) sandwiched between the two outer mandrel members, and capable of being withdrawn in the lengthwise direction from between the two outer mandrel members after the hollow structure has been formed; and a tape (detachable member) formed from a low-friction material and adhered to one or more of the contact surfaces between the two outer mandrel members and the center mandrel member.

Assembled mandrel and method for producing hollow structure

A design method for a semiconductor integrated circuit, includes: a first calculating step; a second calculating step; and a setting step. The first step is a step of calculating a consumption current amount of a layout target circuit based on circuit information. The second calculating step is a step of calculating a suppliable current amount per unit area in a region where a power can be supplied from a power wiring line. The setting step is a step of setting a cell size of the layout target circuit based on the consumption current amount so that a consumption current amount per unit area of the layout target circuit is smaller than the suppliable current amount per unit area.

Method, design program and design support device for semiconductor integrated circuit, and semiconductor integrated circuit

A method of designing a semiconductor device is provided. According to the method, a group of cells that is a target of clock distribution is placed. After the group of cells is placed, a plurality of clock driver cells for driving the clock are placed such that each clock driver cell is prohibited from overlapping with a prohibited region of a predetermined size surrounding another clock driver cell.

Method and program for designing semiconductor device

A semiconductor device having a plurality of wiring layers in a multi-layered structure, includes an inner area at a surface and a pad area surrounding the inner area therein, and further includes a device fabricated below the pad area. The device is comprised of at least one of a bypass capacitor, a protection device, and an input/output device. For instance, the bypass capacitor is comprised of metal wire layers arranged below the pad area.

Semiconductor device and method of fabricating the same

A resistor element according to the present invention comprises a resistive layer provided on a semiconductor substrate through a first insulating film, a first wiring layer provided on the resistive layer through a second insulating film, a second wiring layer provided on the first wiring layer through a third insulating film, a first contact region including a plurality of contacts and provided in the second insulating film and the third insulating film, for electrically connecting the resistive layer to the second wiring layer and a second contact region including a plurality of contacts and provided in the second insulating film, for electrically connecting the resistive layer to said first wiring layer. The contacts of the second contact region are arranged on and along a periphery of a polygonal shape having a center registered with a center point of the first contact region.

Growing community of inventors

Tokyo, Japan

Makoto Nonaka