Kabushiki Kaisha Toshiba

Tokyo Shibaura Denki Kabushiki Kaisha

Sumitomo Wiring Systems, Limited

Kabushiki Kaisha Meidensha

Kandenko Co., Ltd.

Makoto Noda

Tadahiro Kuroda

Kenichi Okada

Hirotugu Kinoshita

Yasuhiko Onishi

Shuzo Tanigaki

Fumihiro Itano

Yoshinao Okawa

Yoshihiro Murano

Isao Ito

Kiyohito Mizuide

Takeshi Uesugi

Masanori Miyamoto

Kazuo Funabashi

Kazuhiro Suda

Masaaki Hoko

Kiyoshi Nagasawa

Yoshiyuki Ema

The semiconductor device includes a circuit, such as, an ECL circuit for comparing input signals with a reference potential determined as a circuit threshold value and outputting an output signal according to the comparison result. The semiconductor device further includes a switching circuit for switching the reference potential level between ordinary operation and burn-in operation of the ECL circuit. The time required for the burn-in operation can be reduced markedly.

Semiconductor device and burn-in method thereof

The invention relates to a rotating electric machine including a coil of a wire having thereon an insulating coating comprising a polybenzimidazole. This rotating electric machine is stably maintained for a long time in dielectric strength even under a highly radioactive environment, due to the use of the special insulating coating. With this, the rotating electric machine can be driven stably for a long time. The invention further relates to another rotating electric machine including (a) a rotor having a rotating shaft; (b) a bearing for supporting the rotating shaft; and (c) a grease applied to the bearing. This grease contains (1) a polyphenyl ether having at least three aromatic rings in the molecule and (2) a urea. The rotor of this rotating electric machine is stably supported in the bearing for a long time even under a highly radioactive environment, due to the use of the special grease. Thus, this rotating electric machine can also be rotated stably for a long time.

Rotating electric machine usable in radioactive environment

A semiconductor integrated circuit device of a standard cell system of this invention includes a cell array constituted by linearly arranging a plurality of cells each having a predetermined unit logical function. A Vcc power supply line and a GND power supply line are formed of a first aluminum layer, to supply a power supply voltage to the cells in the cell arrays. Power supply buses formed of a second aluminum layer are arranged on both the ends of the Vcc power supply line and the GND power supply line through a via hole, in a direction perpendicular to the Vcc power supply line and the GND power supply line. A Vcc power supply line and a GND power supply line formed of a third aluminum layer are arranged on the Vcc power supply line and the GND power supply line, at a central portion of the cell array, through a via hole, and extend in the same direction as the Vcc power supply lines and the GND power supply line, both mode of the first aluminum layer. Two systems of GND power supply lines allow a decrease in current density.

Semiconductor integrated circuit device of standard cell system

The basic cells of a parallel multiplier are arranged into arrays corresponding in number to the number of bits of multiplier data Y and multiplicand data X. Multiplicand data supply lines supply bit data Xi corresponding to the basic cell of the multiplicand data X, its inverted data Xi, bit data Xi-1 one digit lower than said corresponding bit, and its inverted data Xi-1 to each of the basic cells. Decoders decode multiplier data Y based on the Booth's algorithm. These decoders supply a prescribed select signal to the basic cells. The basic cells comprise a selecting circuit for selectively inputting one of data Xi, Xi, Xi-1, Xi-1 and '0' according to the select signal from the decoders, and a full adder. The full adder receives the data input by the selecting circuit as the augend data and receives the addend and carry data from the previous row of basic cells. The full adder adds the augend, addend and carry data, and outputs sum and carry data.

Parallel multiplier utilizing Booth's algorithm

A microcomputer which is set to a power-save mode by an external signal or an output signal from an instruction decoder, and is provided with a flip-flop circuit which is set when microcomputer is set to a power-save mode and is reset upon receipt of an external interruption signal or reset signal, and sends forth a power-save output signal.

Microcomputer with power-save output instructions

A static memory device includes memory cells arranged in the form of a matrix. The memory cells are each formed of a flip-flop circuit and first and second MOS transistors whose current paths are each coupled between a corresponding one of first and second bistable output nodes of the flip-flop circuit and a corresponding one of paired digit lines and whose gates are coupled to first and second word lines, respectively.

Static semiconductor memory device

Growing community of inventors

Yokohama, Japan

Makoto Noda