Spansion Llc.

Fujitsu Corporation

Fujitsu Vlsi Limited

Kyushu Fujitsu Electronics Limited

Makoto Niimi

Takaaki Furuyama

Kenji Nagai

Masahiro Niimi

Yoshihiro Takemae

Masaru Yano

Yoshiharu Kato

Takaaki Suzuki

Satoru Kawamoto

Shoichi Kawamura

Shigemasa Ito

Hideaki Kawai

Toyonobu Yamada

Norikatsu Suzuki

Masato Kaida

A nonvolatile memory devicecapable of preventing interference between a read operation and a rewrite operation, and capable of preventing malfunctions that may occur in the event the read operation and the rewrite operation are performed simultaneously between memory blocks is provided. The nonvolatile memory deviceis provided with a plurality of banks, a rewrite control unitto which a first power source line VCCand a first ground line VSSare connected and which is adapted to control a rewrite operation with respect to a bank i, and a read control unitto which a second power source line VCCand a second ground line VSSare connected and which is adapted to control a read operation with respect to a bank j, wherein the rewrite control unitand the read control unitare arranged so as to be spaced from each another.

Nonvolatile memory device having a plurality of memory blocks

In the storage device of the invention, latch control is performed on a series of signals in response to latch control signals. Latch control terminals are provided to which the latch control signals are input respectively and a plurality of signal terminals to which a series of signals are input. Herein, a plurality of latch circuits is provided so as to correspond to the plurality of signal terminals, respectively. The plurality of latch circuits are located within a specified distance from their associated signal terminals respectively and within a specified distance from the latch control terminals. The delays of signal transmission from the signal terminals to their associated latch circuits can be equalized and the delays of signal transmission from the latch control terminals to which the latch control signals for executing latch control are input to the latch circuits can be equalized. This contributes to a reduction in the skew of the latch characteristics of the signals.

Time reduction of address setup/hold time for semiconductor memory

A semiconductor device () is provided which includes a regular cell array unit (), a redundant cell array unit () that is provided in relation to the regular cell array unit (), and a PGM/ER state machine () that controls reprogramming in which, when programming of a sector in the regular cell array unit fails (step S), data involved in the programming that fails and data already stored in the sector in the regular cell array unit are written (step S) into the redundant cell array unit (). Since reprogramming is performed to write the data already written in the sector as well as the data involved in the programming that fails into the redundant cell array unit (), data loss can be prevented and data can be secured, thereby increasing the reliability of the system.

Semiconductor device and program data redundancy method therefor

The present invention is a memory circuit, comprises: a memory cell array including a plurality of bit lines, a plurality of word lines, and a plurality of memory cells disposed in the positions of intersection between the bit lines and the word lines; and a page buffer, which is connected to the bit line and which detects memory cell data by judging with predetermined sense timing the potential of the bit line when a pre-charged bit line potential is discharged in accordance to a cell current of a selected memory cell. Further the sense timing differs in accordance with the position of the selected memory cell in the memory cell array.

AC sensing method memory circuit

A semiconductor integrated circuit device is intended to prevent generation of an unnecessary leak current and hence to reduce power consumption. In the semiconductor integrated circuit device comprising: a current path which is formed between a predetermined power source terminal (or a predetermined power source pad) and a predetermined low potential power source line, a comparison circuit for comparing a node potential in the current path with a predetermined threshold voltage to thereby detect whether the voltage applied to said power source terminal is a voltage which is larger than an upper limit value of the terminal voltage, a signal generation circuit for generating a predetermined logic signal when the states of some designated control terminals satisfy a combination which is determined in advance, if the logic state of an output signal of said signal generation circuit is a predetermined logic state when said comparison circuit has detected that the voltage applied to the power source terminal is a voltage which is larger than an upper limit value of the terminal voltage, a circuit equipped with a predetermined function mounted on the chip is activated, the semiconductor integrated circuit device being characterized by comprising ON/OFF circuit for turning on and off said current path in accordance with the logic state of the output signal of said signal generation circuit.

Semiconductor integrated circuit device capable of reducing power

A semiconductor memory device has an oscillator unit for generating refresh pulses, a refresh address detection unit for detecting refreshed addresses and outputting a predetermined signal upon the completion of the refreshing of all addresses, and an output control unit for continuing a self-refresh mode to refresh all addresses according to the signal from the refresh address detection unit, before releasing the self-refresh mode in response to an external signal. Therefore, the refresh operation is continued until all cells are refreshed, thereby data stored in the semiconductor memory device is not lost and is correctly refreshed.

Semiconductor memory device having self-refresh function

Growing community of inventors

Nagoya, Japan

Makoto Niimi