Sony Corporation

Kabushiki Kaisha Toshiba

Accenture Global Solutions Limited

Sony Group Corporation

Astellas Pharma Gmbh

Murai Associates Corporation

Makoto Murai

Yuji Takaoka

Hiroyuki Yamada

Yoshimichi Harada

Takuya Kudo

Kazuki Sato

Shin Moriga

Motoaki Hayashi

Atsushi Suyama

Takayuki Tanaka

Takuya Nakamura

Kiyoshi Wagai

Tatsuaki Sekigawa

Makoto Imai

Hiroaki Tasaki

Shigeki Amano

Tatsunobu Yoshioka

Kana Nagayoshi

The present disclosure describes a method of controlling a manufacturing system using multivariate time series and includes storing recording data as a plurality of time series, each time series having a first recorded value and a final recorded value, interpolating, within a first time window, missing values in the plurality of time series using a Bayesian model, the missing values falling between a first and an end time of the respective time series, storing the interpolated values as prediction data, each interpolated value including an uncertainty, loading recorded data of a second time window, loading prediction data of the second time window, predicting, using the Bayesian model, values for each time series that is absent recorded data and prediction data, storing the predicted values, each prediction value including an uncertainty, and adjusting a device that generates the recorded data based on the prediction values within the second time window.

Prediction method and system for multivariate time series data in manufacturing systems

The present disclosure describes a computer-implemented method for detecting anomalies during lot production, wherein the products within a production lot are processed according to a sequence of steps that include manufacturing steps and one or more quality control steps interspersed among the manufacturing steps, the method comprising: obtaining process quality inspection data from each of the one or more quality control steps for a first production lot; obtaining product characteristics data for the products in the first production lot after the final step in the sequence; training a Gaussian process regression model using the process quality inspection data and the product characteristics data from the first production lot; generating a predictive distribution of the product characteristics data using the Gaussian process regression model that uses a bathtub kernel function; obtaining process quality inspection data from each of the quality control steps for a second production lot; identifying anomalies in the second production lot using the predictive distribution of the product characteristics data and the process quality inspection data from the second production lot; if no anomalies are detected in the second production lot, updating the Gaussian process regression model using the process quality inspection data from the second production lot; setting target values for one or more values in the process quality inspection data based on the predictive distribution of the product characteristic; and adjusting settings of one or more manufacturing steps based on the target values.

Anomaly detection method and system for manufacturing processes

In a semiconductor device, a first package is provided with a first substrate under which a semiconductor chip configured to output a signal and a first wiring electrically connected to the semiconductor chip are arranged. A second package is provided with a second substrate above which a processing circuit configured to process the output signal, a second wiring electrically connected to the processing circuit, and an encapsulant configured to seal the processing circuit are arranged, the semiconductor chip and the encapsulant being arranged to face each other in a non-contact manner. A connection portion electrically connects the first wiring and the second wiring.

Semiconductor device and imaging apparatus

The present disclosure describes a method of controlling a manufacturing system using multivariate time series, the method comprising: recording data from one or more devices in the manufacturing system; storing the recorded data in a data storage as a plurality of time series, wherein each time series has a first recorded value corresponding to a first time and a final recorded value corresponding to an end of the time series; interpolating, within a first time window, missing values in the plurality of time series using a Bayesian model, wherein the missing values fall between the first and end time of the respective time series; storing the interpolated values as prediction data in a prediction storage, wherein the interpolated values include the uncertainty of each interpolated value; loading the recorded data that fall within a second time window from the data storage; loading prediction data from the prediction storage that fall within the second time window and for which no recorded data are available; optimizing the parameters of the Bayesian model using the loaded recorded data and the prediction data; predicting, using the Bayesian model, values for each of the time series for which loaded recorded and prediction data are not available; storing the predicted values as prediction data in the prediction storage, wherein the prediction values include the uncertainty of each prediction value; and adjusting one or more of the devices that generate the recorded data based on the prediction data within the second time window.

In the semiconductor device, a first package is provided with a first substrate under which a semiconductor chip configured to output a signal and a first wiring electrically connected to the semiconductor chip are arranged. A second package is provided with a second substrate above which a processing circuit configured to process the output signal, a second wiring electrically connected to the processing circuit, and an encapsulant configured to seal the processing circuit are arranged, the semiconductor chip and the encapsulant being arranged to face each other in a non-contact manner. A connection portion electrically connects the first wiring and the second wiring.

A semiconductor chip includes a chip body and a plurality of solder-including electrodes provided on an element-formation surface of the chip body. A packaging substrate includes a substrate body, a plurality of wirings, and a solder resist layer, in which the plurality of wirings and the solder resist layer are provided on a front surface of the substrate body. The solder resist layer is provided as a continuous layer on the front surface of the substrate body and the plurality of wirings, and has an aperture on each of the plurality of wirings. The plurality of solder-including electrodes include at least one gap control electrode. The at least one gap control electrode includes a columnar metal layer and a solder layer in order named from side on which the chip body is disposed, and includes an overlap region where the columnar metal layer and the solder resist layer overlap each other, along part or all of an aperture end of the aperture.

Semiconductor device with a gap control electrode and method of manufacturing the semiconductor device

A semiconductor chip includes a chip body and a plurality of solder-including electrodes provided on an element-formation surface of the chip body. A packaging substrate includes a substrate body, and one or more conductive layers and a solder resist layer that are provided on a front surface of the substrate body. The solder resist layer is provided as a continuous layer on the front surface of the substrate body and the one or more conductive layers, and has one or more apertures on each of the one or more conductive layers. The plurality of solder-including electrodes include two or more first electrodes having a same function other than a function of power supply. The one or more conductive layers include a continuous first conductive layer. The two or more first electrodes are connected to the continuous first conductive layer. The one or more apertures are confronted with the respective two or more first electrodes.

Semiconductor device and method of manufacturing the same

A semiconductor chip includes a chip body and a plurality of solder-including electrodes provided on an element-formation surface of the chip body. A packaging substrate includes a substrate body, and a plurality of wirings and a solder resist layer that are provided on a front surface of the substrate body. The plurality of solder-including electrodes include a plurality of first electrodes and a plurality of second electrodes. The plurality of first electrodes supply a first electric potential, and the plurality of second electrodes supply a second electric potential different from the first electric potential. The plurality of first electrodes and the plurality of second electrodes are disposed alternately in both a row direction and a column direction, in a central part of the chip body. The plurality of wirings include a plurality of first wirings and a plurality of second wirings. The plurality of first wirings connect the plurality of first electrodes, and the plurality of second wirings connect the plurality of second electrodes.

Semiconductor chip mounted on a packaging substrate

Provided is a semiconductor device that includes a semiconductor chip, and a packaging substrate on which the semiconductor chip is mounted. The semiconductor chip includes a chip body and a plurality of solder-including electrodes that are provided on an element-formation surface of the chip body. The packaging substrate includes a substrate body, and a plurality of wirings and a solder resist layer that are provided on a front surface of the substrate body. The solder resist layer is provided as a continuous layer on the front surface of the substrate body and the plurality of wirings, and has an aperture on each of the plurality of wirings. The aperture has a planar shape elongated in a lengthwise direction of the wiring inside the aperture, with a length of the aperture adjusted in accordance with a thermal expansion coefficient of the packaging substrate.

Semiconductor device with less positional deviation between aperture and solder

Disclosed is a pharmaceutical composition comprising a complex between solifenacin or a pharmaceutically acceptable salt thereof and an ion exchange resin, and an acrylic based polymer.

Pharmaceutical composition comprising solifenacin

Disclosed herein is a semiconductor device, including: a mount body having a first principal surface on which a wiring pattern is formed; a semiconductor chip mounted above the principal surface of the mount body on which the wiring pattern is formed; an underfill material filled between the mount body and the semiconductor chip, thereby forming a fillet in an outer peripheral portion of the semiconductor chip; and an introduction portion formed outside a side portion, along which the fillet is formed so as to be longest, of four side portions which measure a chip mounting area, on the mount body, onto which the semiconductor chip is mounted, the introduction portion serving to introduce the underfill material between the mount body and the semiconductor chip.

Semiconductor device and a method of manufacturing the same

Provided is a semiconductor device, including: a first substrate that includes a first wiring; a second substrate that is disposed facing the first substrate and includes a second wiring, the second wiring being connected to the first wiring through a connection terminal, and the second substrate being smaller in area than the first substrate; a first resin layer that is filled in a gap between the first substrate and the second substrate and covers a region, on the first substrate, in an outer periphery of the second substrate; an organic film pattern that is provided on the first substrate and surrounds the first resin layer; and a second resin layer that covers the first substrate, the organic film pattern, the first resin layer, and the second substrate.

Semiconductor device and method of manufacturing semiconductor device

A semiconductor device includes: a mount body; a semiconductor chip mounted on the mount body via projecting connecting terminals; and a filling resin filled between the mount body and the semiconductor chip to seal the connecting terminals, the filling resin being retained inside the semiconductor chip in such a way as not to run out of at least one side portion in four side portions defining an outer peripheral portion of the semiconductor chip.

Semiconductor device and method of fabricating the same

A semiconductor device includes: a mounted body in which a wiring pattern is formed on a first main surface; a semiconductor chip mounted on the surface of the mounted body on which the wiring pattern is formed; an underfill material which is filled between the mounted body and the semiconductor chip and forms a fillet on an outer peripheral part of the semiconductor chip; and an injection section which is disposed on the mounted body and on an outside of a side section, on which the fillet is formed to be longest, of four side sections defining a chip mount area on which the semiconductor chip is mounted, and guides the underfill material to between the mounted body and the semiconductor chip.

Semiconductor device and manufacturing method of the semiconductor device

A moving image for a game which is conducted at a specific location are distributed in real time, so as to implement a network participation type game which has an enhanced feeling of reality. By this game being distributed as a moving image in real time via a transmission line such as the Internet or a telephone line network, and by an unspecified number of people entering into conversation via terminal devices which receive this game, the game conducted at the specific location is executed, and thereby the feeling of reality is increased. Furthermore by including, in this game which is distributed as a moving image, reference time information which absorbs the time difference between the game which is conducted at the specific location and the game which is conducted upon the terminal device, players can participate in this game simultaneously in real time.

Growing community of inventors

Tokyo, Japan

Makoto Murai