Hitachi, Ltd.

Ricoh Company, Ltd.

Makoto Morioka

Kazuhiro Ito

Yuichi Ono

Kazuhiro Kurata

Masao Kawamura

Tomoyoshi Mishima

Mitsuhiro Mori

Yasuhiro Shiraki

Yoshifumi Katayama

Masahiko Kawata

Kiichi Ueyanagi

Takao Kuroda

Yasushi Sawada

Hirobumi Ouchi

Hiroshi Matsuda

Susumu Takahashi

Eiichi Maruyama

Masao Yamane

Sachio Ishioka

Masaaki Aoki

Kenji Hiruma

Yoshimasa Murayama

Shigeo Goto

Masahiro Ichiki

Takeo Takahashi

Mitshiuro Mori

Ginro Takemura

Youichi Yasuda

Makoto Sakamoto

Yasushi Koga

Two image processing systems and an image processing method are provided. One of the image processing systems includes a first unit configured to output a portion of input image data, a second unit configured to transform a coordinate of input image data, and a third unit configured to output the image data processed by the first unit and the second unit as video data to be displayed on a display. The other one of the image processing system further includes a fourth unit configured to combine input image data of a plurality of images to output one piece of image data. The image processing method includes outputting a portion of input image data, transforming a coordinate of input image data, and outputting the image data as video data to be displayed on a display.

Image processing system and image processing method

A write strategy circuit and a write strategy method for capturing data are disclosed. A strategy clock generator generates a strategy clock signal based on a channel clock signal. A phase controller produces a capturing channel clock signal by controlling a phase of the channel clock signal in synchronization with the strategy clock signal. A data capturing circuit captures the data in synchronization with the capturing channel clock signal. A phase determination circuit determines whether a length of the data corresponds to a predetermined value. A strategy correction circuit applies a predetermined strategy correction to the data based on the strategy clock signal. In this case, the phase controller controls the phase of the channel clock signal based on a determination result of the phase determination circuit. An optical disk apparatus using the write strategy circuit or the write strategy method is also disclosed.

Write strategy circuit, write strategy method, and optical disk apparatus

A compound semiconductor structure in the form of a superlattice film with effectively graded average composition, comprising an alternating lamination of two kinds of layers of different composition to form pairs of layers, the ratio of the thickness of one layer to the thickness of the other in said pairs of layers being gradually varied in the direction of thickness throughout successive pairs, thereby the average composition being effectively graded throughout the pairs. In a hetero-junction field effect transistor, the layer of effectively graded composition is used between a semiconductor layer making low resistance contact with a current-supplying electrode and a semiconductor layer where a two dimensional channel is to be formed. In case of AlGaAs/GaAs system, the Al composition is varied. When the superlattice film is heat-treated, Al in the AlGaAs layer diffuses into the GaAs layer, yielding a film with actually smoothly graded Al mole fraction.

Compound semiconductor structure and process for making same

An epitaxial crystal grown layer structure which permits, on an In-doped GaAs substrate, which will be industrially used in large quantities, the growth of an epitaxial layer having the same good quality as the epitaxial layer grown on an undoped GaAs substrate.

Semiconductor device having strained superlattice buffer layers with

Disclosed is a photo-detective semiconductor device having, on a predetermined semiconductor substrate, at least a first semiconductor layer which exhibits a first conductivity type, a second semiconductor layer which is disposed on said first semiconductor layer, which has a forbidden band gap greater than that of said first semiconductor layer and which exhibits the first conductivity type, and a p-n junction which is formed by a region disposed in said second semiconductor layer and exhibiting a second conductivity type; characterized by comprising a third semiconductor layer which is disposed on said second semiconductor layer, which exhibits the first conductivity type and which has a surface protective function. The third semiconductor layer is usually made of a group III-V compound semiconductor of a quaternary system. By way of example, in a case where the first semiconductor layer is formed of InGaAsP and where the second semiconductor layer is formed of InP, the third semiconductor layer is made of InGaAsP, InGaAs or the like. A photo-detective semiconductor device of low dark current can be provided.

Photo semiconductor device

There is disclosed a semiconductor device comprising at least first and second semiconductor layers positioned to form a hetero-junction therebetween, such a hetero-junction being adapted to form a channel, means for controlling carriers, and source and drain areas on opposite edges of the channel, wherein the first and second semiconductor layers formed between the source and drain regions have an area containing only 10.sup.16 cm.sup.-3 or less of an impurity; the first semiconductor layer has a wider forbidden band than that of the second semiconductor layer; and further including at least one semiconductor layer having a higher activation efficiency of impurities than that of the first semiconductor layer, with such at least one semiconductor layer being located on the side of the first semiconductor layer not in contact with the second semiconductor layer. A multi-quantum well structure may be used as the higher impurity activation efficiency semiconductor layer. The electrical resistance in the semiconductor area constituting the source and drain regions can be lowered by utilizing such a higher impurity activation efficiency semiconductor layer.

Heterojunction FET with doubly-doped channel

A semiconductor member has a structure wherein a first semiconductor layer is held between second and third semiconductor layers which have forbidden band widths greater than a forbidden band width of the first semiconductor layer, and wherein only the second semiconductor layer which is formed on a side of the first semiconductor layer close to a substrate is doped with impurities. The semiconductor member constructs the depletion type with the first and second semiconductor layers, and the enhancement type with the first and third semiconductor layers. A semiconductor device can be properly formed in the enhancement or depletion type by selectively connecting the semiconductor layers.

Semiconductor member and semiconductor device employing the same

An optical semiconductor device includes a light emitting element disposed on a silicon sub-mount having a light receiving element formed in a surface region. By virtue of integral arrangement of the light emitting element and the light receiving element, a single lens can be used for both optical transmission and optical reception, whereby an optical communication system can be manufactured very inexpensively. Further, transmission and reception can be carried out simultaneously.

Optical semiconductor device

In a prior-art injection type light emitting device which is constructed so that a predetermined range of a p-n junction formed by a semiconductor substrate and an epitaxial layer provided thereon may radiate, a radiation region in the p-n junction becomes larger in area than the region into which current is introduced, on account of the current spreading phenomenon. The construction of a light emitting device free from the phenomenon and a method for manufacturing the light emitting device are disclosed.

Light emitting devices

A light emitting semiconductor device wherein a p-n junction is defined by a ditch and wherein the ditch either extends to a low resistance layer or is away from the low resistance layer at most 1/2 of the width of the ditch is disclosed. It has the merit that the near field pattern is much more uniform than in a prior-art device.

Light emitting semiconductor device

A light emitting element made of a group III - V compound semiconductor has a p-n junction and a hetero-junction which are identical; the mixing ratio (band gap) of a p-type layer on the light emitting side is sufficiently smaller than that of an n-type layer on the opposite side. The semiconductor light-emitting element is especially useful as a light source, for optical communications, photoexcitation, etc.

Semiconductor light-emitting element

A light emitting semiconductor diode comprises a first semiconductor region having a first conductivity type and a narrow forbidden band gap, a second semiconductor region, disposed on the first semiconductor region, having the first conductivity type and a low impurity concentration, a third semiconductor region, disposed on the second semiconductor region, having a second conductivity type which is opposite to the first conductivity type, and an ohmic contact disposed on the surface of the first semiconductor region, which is opposite to the second semiconductor region. The surface has a plurality of holes extending from the outer surface through the first semiconductor region toward a p-n junction between the second and third semiconductor regions, which holes are filled with a highly reflective metal having a high thermal conductivity.

Light emitting semiconductor diode

In order to eliminate non-uniformity in the temperature within the plane of a substrate that causes dispersions or variations in the characteristics of a grown layer during liquid phase epitaxial growth and to produce a grown layer having uniform characteristics, an apparatus for crystal growth according to the invention holds a substrate on a jig so that a flat surface of the substrate is arranged tangentially to an isothermal plane within the jig and aslant with respect to any position perpendicular or parallel to the axis or the center plane of the jig. Where a multiplicity of substrates are set, they are held on at least two flat surfaces which are tangential to an identical isothermal plane and which have different slopes.

Apparatus for crystal growth

In a method for making a light emitting device having hemispherical dome type geometry, a p-conductivity type and then an n-conductivity type layer are successively grown epitaxially on a substrate made of a mixed compound semiconductor crystal having a band gap wider than the two above-mentioned layers. A surface portion of these epitaxially grown layers, which is not covered by a mask deposited on the n-conductivity type layer at a position where a p-n junction is to be formed, is doped with p-conductivity type impurities so that a small n-conductivity type region is surrounded by a region converted into p-conductivity type. The other side of the crystal is formed into a hemispherical shape so that the n-conductivity type region is located at the central portion of the hemisphere.

Growing community of inventors

Tokyo, Japan

Makoto Morioka