Ricoh Company, Ltd.

Makoto Matsushima

Katsuhiko Manabe

Tomonari Katoh

Minoru Sugiyama

Tadayoshi Ueda

Ryo Fukui

A PWM signal generating circuit outputs a stable PWM signal for increasing and decreasing a duty ratio at a predetermined rate within a predetermined period without requiring an improvement of a process capacity of a CPU as compared to a conventional PWM signal generating circuit. The PWM signal generating circuit consists of a plurality of circuit elements each of which outputs a digital signal. A first counter circuit periodically changes a PWM signal output therefrom into an active state. A second counter circuit changes the PWM signal, which has been changed into the active state by the first counter circuit, into an inactive state within each cycle. The second counter circuit increases and decreases an active-to-inactive time period from a time when the PWM signal is changed into the active state to a time when the PWM signal is changed into the inactive state.

Pulse width modulation signal generating circuit

A DC converter with a halt mode setting is disclosed for preventing the occurrence of over-current while alleviating the increase in the size of circuits, along with a method for setting up such a halt mode. The DC converter includes a semiconductor switch, a clock generator for outputting a clock signal to a gate of the semiconductor switch to be utilized for controlling an on/off time of the semiconductor switch such that a predetermined power is output from the generator, and a drive circuit for switching the semiconductor switch to the continuous-on state according to a halt mode setting requirement regardless of the clock signal, when the semiconductor switch, normally repeating on/off operations responsive to the clock signal, is in its off-state.

DC converter with halt mode setting means

A PWM signal generating circuit outputs a stable PWM signal for increasing and deceasing a duty ratio at a predetermined rate within a predetermined period without requiring an improvement of a process capacity of a CPU as compared to a conventional PWM signal generating circuit. The PWM signal generating circuit consists of a plurality of circuit elements each of which outputs a digital signal. A first counter circuit periodically changes a PWM signal output therefrom into an active state. A second counter circuit changes the PWM signal, which has been changed into the active state by the first counter circuit, into an inactive state within each cycle. The second counter circuit increases and decreases an active-to-inactive time period from a time when the PWM signal is changed into the active state to a time when the PWM signal is changed into the inactive state.

Pulse with modulation signal generating circuit

An amplifying circuit includes a battery power source, a regulator that regulates an output of the battery power source and generates a reference voltage, and a signal ground generating device that generates and outputs a signal ground by changing the reference voltage in accordance with deterioration detected from the battery power source. An operational amplifier is provided to amplify and output a signal having prescribed waveform to be input to a speaker. The operational amplifier uses a battery power source as a driving power source of its own. The signal ground is positioned at a center of vibration amplitude of the waveform.

Amplifying circuit, speaker system, and mobile information terminal employing amplifying circuit

A level-controlling unit consisting of an inverter controls a level of a given pulse signal, the level controlling being performed in a predetermined manner. An analog-signal producing unit consisting of a low-pass filter produces an analog signal by integrating the pulse signal having undergone the level controlling. An analog-signal processing unit consisting of A-D converter processes the analog signal with a dynamic range thereof so as to supply a digital signal, the dynamic range being defined by a predetermined reference level. The predetermined manner is such that a substantial possible level variation extent of the analog signal received by the analog-signal processing unit corresponds to the dynamic range.

Signal processing circuit with built-in dynamic range matching

An image processing apparatus includes: a first transforming device for transforming encoded data into discrete cosine transform coefficient data segmented into processing blocks, each block being formed of a matrix of m.times.n pixels; and a setting device for setting the values of M and N defining the size of a matrix forming each processing block used in inverse discrete cosine transform. The image processing apparatus also includes a data preparing circuit for adding discrete cosine transform coefficient data to, or deleting discrete cosine transform coefficient data from, a high-frequency domain of the discrete cosine transform coefficient data and segmented into processing blocks, each block being formed of a matrix of m.times.n pixels, and for preparing discrete cosine transform coefficient data segmented into processing blocks, each block being formed of a matrix of M.times.N pixels; a second transforming device for subjecting the discrete cosine transform coefficient data prepared by the data preparing circuit to inverse discrete cosine transform, so that image data can be output; and an outputting device for outputting image data output from the second transforming device and segmented into processing blocks as continuous image data.

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Hyogo-ken, Japan

Makoto Matsushima