Hitachi, Ltd.

Hitachi Vlsi Engineering Corp.

Makoto Kuwata

Toshiyuki Sakuta

Toshiaki Minami

Akira Masaki

Nobuo Tamba

Tomofumi Hokari

Takeshi Isezaki

Nobuaki Kitamura

Ryuichi Satomura

Masatoshi Tsuge

A semiconductor device capable of determining plural transfer speeds with a small-scale circuit, and an information processing system having the semiconductor device are provided. The semiconductor device has a frequency determining circuit that receives a data signal on which plural transfer speeds can be set and that determines a transfer speed of the data signal. The frequency determining circuit latches the data signal at each of plural timings continuing with a predetermined interval, detects how many times a data switching occurs consecutively, based on the latched plural data, and determines the transfer speed of the data signal from the result of the detection.

Semiconductor device and information processing system

A semiconductor device or semiconductor device package for transmitting a plurality of differential signals, the reliability of which hardly deteriorates. The semiconductor device is an area array semiconductor device in which a plurality of lands (external terminals) including a plurality of lands for transmitting a plurality of differential signals are arrayed in a matrix pattern in the back surface of a wiring substrate. Some of the lands are located in the outermost periphery of the matrix pattern. Some others of the lands are located inward of the outermost periphery of the matrix pattern and in rows next to the outermost periphery. The spacing between lands in a second region between the lands located in the rows next to the outermost periphery and the side surface of the wiring substrate is larger than in a first region in the outermost periphery.

Semiconductor device and package wiring substrate with matrix pattern external terminals for transmitting a differential signal

In a semiconductor device having the upmost wiring layer comprised of aluminum and the wiring layer immediately below it comprised of copper, the upmost wiring layer is made thicker than the wiring layer immediately below it so that the upmost wiring layer is lower in sheet resistance than the wiring layer immediately below it. Multiple ring power lines VR and pads PD are formed of the upmost wiring layer, and the ring power lines VR and the pads PD are connected respectively through power lines VLBof the upmost wiring layer. Consequently, the voltage drop on the power feed path from the pads PD to the ring power lines VR can be reduced and the power conduction from the pads PD to the ring power lines VR can be stabilized.

Semiconductor device

In a semiconductor device having the upmost wiring layer comprised of aluminum and the wiring layer immediately below it comprised of copper, the upmost wiring layer is made thicker than the wiring layer immediately below it so that the upmost wiring layer is lower in sheet resistance than the wiring layer immediately below it. Multiple ring power lines VR and pads PD are formed of the upmost wiring layer, and the ring power lines VR and the pads PD are connected respectively through power lines VLB of the upmost wiring layer. Consequently, the voltage drop on the power feed path from the pads PD to the ring power lines VR can be reduced and the power conduction from the pads PD to the ring power lines VR can be stabilized.

A programmable two-line, two-phase logic array has a plurality of inputs, each having two input signals operating in two phases and memory cells provided at an intersection of the input signal lines and output lines corresponding to at least one function that cross the input lines. The memory cells are capable of being written in the fabrication process or by a field programming process that addresses the contact points at which the input and output lines cross. The two-line, two-phase logic circuit can be attained by the same technique as that used for attaining a conventional PLA without designing circuitry based on a conventional synchronous logic beforehand followed by replacing it with a two-line, two-phase circuit.

Programmable two-line, two-phase logic array

In a clock wiring of a semiconductor integrated circuit device or a printed wiring, a shield clock wiring to be connected with the same drive source as a drive source to be connected with the clock wiring is laid adjacent to the whole or partial length of the clock wiring.

Growing community of inventors

Akiruno, Japan

Makoto Kuwata