Kioxia Corporation

Kabushiki Kaisha Toshiba

Toshiba Memory Corporation

Makoto Kuribara

Katsuhiko Ueki

Yoshihisa Kojima

Shin Takasaka

Rintaro Arai

Takeshi Tomizawa

Akiyoshi Hashimoto

Kenji Takahashi

A memory system controls timing of a refresh operation. The memory system includes a non-volatile memory including first and second memory cell units and a controller connectable to a host. The controller stores an execution time of write and erase operations with respect to the first memory cell unit, receives from the host power-on time information indicating a power-on time of the memory system when the memory system is powered on, determines a first time period from a last write or erase operation with respect to the first memory cell unit based on the stored execution time and the power-on time, determines an execution time of the refresh operation of transferring data stored in the first memory cell unit to the second memory cell unit based on the first time period, and starts the refresh operation at the determined execution time.

Memory system that controls timing of refresh operation

According to one embodiment, a memory system includes a non-volatile memory and a controller. The memory includes a plurality of storage areas. Each of the storage areas includes a plurality of memory cells to which threshold voltages are set in accordance with data. The controller acquires a first threshold voltage distribution of memory cells in a first storage area of the storage areas. The controller acquires a second threshold voltage distribution of memory cells in a second storage area of the storage areas. The controller detects non-normalcy in the first storage area or the second storage area from a first divergence quantity between the first threshold voltage distribution and the second threshold voltage distribution.

Memory system and method

According to one embodiment, a storage device includes a nonvolatile memory and a controller. The controller is configured to read data from the nonvolatile memory by applying a read voltage to the nonvolatile memory. The controller is configured to correct the read voltage based on a difference between a measured value of a bit number obtained when the data is read from the nonvolatile memory by applying the read voltage to the nonvolatile memory and an expected value of the bit number.

Storage device and reading method

According to one embodiment, a memory system includes a non-volatile semiconductor memory having a plurality of blocks each including a plurality of memory cells, and a memory controller configured to calculate a bit error rate when reading data from a block of the blocks and obtain an equation representing temporal changes in the bit error rate for the block, and based on the obtained equation, determine, for the block, a timing for performing a next refresh operation by which data that have been written to the block are rewritten.

Memory system and method performed thereby

According to one embodiment, a memory system includes a semiconductor memory and a memory controller. The memory controller writes a first data group in the semiconductor memory and then reads the first data group from the semiconductor memory. The memory controller counts a number of first data and a number of second data based on a comparison of a second data group with a third data group. The memory controller changes a first charge threshold based on the number of first data and the number of second data. The second data group is the first data group at the time of writing to the semiconductor memory. The third data group is the first data group read from the semiconductor memory. The first data is data changed from a first code to a second code. The second data is data changed from the second code to the first code.

Growing community of inventors

Yokohama, Japan

Makoto Kuribara