Seiko Epson Corporation

Hioki Denki Kabushiki Kaisha

Makoto Kudo

Yoshiyuki Miyayama

Yoichi Hijikata

Satoshi Kubota

Katsuya Iida

Keisuke Hashimoto

Hisao Sato

Hirofumi Terasawa

Fumio Narusawa

Tomoyuki Maruyama

A control device includes a processor wherein the processor is configured to: receive designation of one or more frequency components, generate one or more second control signals obtained by reducing at least one of the frequency components from a first control signal, generate one or more third control signals obtained using two control signals among the first control signal and the one or more second control signals, output one control signal among the first control signal, the one or more second control signals, and the one or more third control signals, and generate and output a driving signal to drive a robot based on the one control signal.

Control device and robot system

A data processing device is provided using pipeline architecture to reduce a time loss due to a branch without causing an increase in circuit scale. The data processing device uses pipeline control. The data processing device includes an instruction queue in which a plurality of instruction codes can be fetched, a fetch address operation circuit which calculates a fetch address, a fetch circuit which fetches an instruction code based on the fetch address, and a branch information setting circuit which decodes a branch setting instruction, stores a branch address in a branch address storage register, and stores a branch target address in a branch target address storage register. The fetch address operation circuit compares either a previous fetch address or an expected next fetch address with a value stored in the branch address storage register, and determines a next fetch address to be output, based on the comparison result.

Data processing device and electronic equipment using pipeline control

An integrated circuit device including an internal debug module for on-chip debugging while communicating with a pin-saving debug tool and a CPU, the integrated circuit device comprises; a first debug terminal coupled to a first communication line; a first common control unit that controls using the first communication line for both transmission of a serial data signal corresponding debug data for sending, which is sent and/or received to and/or from the pin-saving debug tool during on-chip debugging and transmission of a run/break state signal, which shows a run state or a break state of the CPU.

Semiconductor integrated circuit device, debug system, microcomputer, and electronic apparatus

An information processing apparatus performing pipeline control includes a first fetch cue fetching a non-branch location instruction, a second fetch cue fetching a branch location instruction, a fetch circuit which carries out arithmetic of a fetch address, fetch it to the first fetch cue or the second fetch cue, and outputs a first fetch cue or a second fetch cue instruction to a decode circuit, a decode circuit which receives and decode an instruction code fetched to the first fetch cue or the second fetch cue, and an execution circuit performing execution of an instruction based on a decoding result, wherein the above-mentioned fetch circuit includes a selective circuit which selects which instruction of the first fetch cue or the second fetch cue to send to the decode circuit based on the execution result of a comparison instruction.

Information processing apparatus, microcomputer, and electronic computer

The data processing device and electronic equipment of the present invention perform pipeline control and include a fetch circuit which fetches instruction codes of a plurality of instructions in instruction queues. A prefix instruction decoder circuit performs a decode processing only on a prefix instruction. The prefix instruction decoder circuit receives the instruction code before decoding, judges whether or not the instruction is a given prefix instruction, and causes a target instruction to modify an information register to store information necessary for decoding a target instruction when the instruction is the given prefix instruction. A decoder circuit receives each of the instruction codes of the instructions other than the prefix instruction as a decode instruction and decodes the decode instruction. When the decode instruction is a target instruction, the target instruction modified by the prefix instruction is decoded based on the target instruction modifying information.

Shift prefix instruction decoder for modifying register information necessary for decoding the target instruction

An object is to provide a microcomputer, electronic instrument and debugging system which can realize an on-chip debugging function through a reduced size of instruction code or a reduced circuit scale. A main monitor section () converts a debugging command into a primitive command. A mini monitor section () transfers data to and from the main monitor section () to execute a primitive command determined based on the receive data. The primitive commands include go, write and read commands. A control register having its address allocated on a memory map in the debugging mode is provided together with a mini monitor RAM. The mini monitor section () serving as a slave is connected to the main monitor section () serving as a master through a half-duplex bidirectional communication line so that transfer data can be fixed-length. The receive data includes a command identifying data. A mini monitor program has been stored in a ROM. The mini monitor section () and main monitor section () use a clock in common to generate a sampling clock while transferring data in the start-stop synchronization.

Microcomputer, electronic equipment and debugging system

The present invention provides a microcomputer that makes it possible to implement a real-time trace on a mass-produced chip using few terminals, acquire trace information from within a specified range, and measure execution times, together with electronic equipment and a debugging system comprising this microcomputer. A trace information output section () outputs trace information for implementing a real-time trace, to four dedicated terminals. It outputs instruction execution status information (DST[2:0]) of the CPU to three terminals and the PC value (DPCO) of a branch destination when an PC absolute branch has occurred, serially to one terminal. A microcomputer () outputs information indicating the start and end of a trace range or execution-time measurement range to DST[] in a predetermined sequence. A debugging tool () determines the start and end of the trace range or execution-time measurement range from the values in DST[

Microcomputer, electronic equipment, and debugging system

An object is to provide a microcomputer, electronic instrument and debugging system which can realize an on-chip debugging function through a reduced size of instruction code of a reduced circuit scale. A main monitor section () converts a debugging command into a primitive command. A mini monitor section () transfers data to and from the main monitor section () to execute a primitive command determined based on the receive data. The primitive commands include go, write and read commands. A control register having its address allocated on a memory map in the debugging mode is provided together with a mini monitor RAM&#x3e; The mini monitor section () serving as a slave is connected to the main monitor section () serving as a master through a half-duplex bidirectional communication line so that transfer data can be fixed-length. The receive data includes a command identifying data. A mini monitor program has been stored in a ROM. The mini monitor section () and main monitor section () use a clock in common to generate a sampling clock while transferring data in the start-stop synchronization.

A PWM control circuit, microcomputer and electronic equipment which can generate high-resolution PWM signals through a small-sized scale of circuit. The PWM control circuit includes a PWM period value setting register, a counter, an edge-point value setting register, a PWM output circuit for varying the level of the PWM signal at a first edge-point, and a delay value setting register provided on low order side of the edge-point value setting register, for specifying a delay time of the first edge-point. The PWM output circuit delays the first edge-point by a period smaller than one clock period of CLK, in accordance with the value in the delay value setting register. This can improve the resolution of the PWM signal. One-bit or two-bit value is stored in the delay value setting register. Based on the stored value, the first edge-point can be delayed by &#xbd;, &#xbc;, 2/4 or &#xbe; clock period.

PWM control circuit, microcomputer and electronic equipment

A microcomputerwith a debug circuitimplemented therein for realizing an on-chip debugging function is mounted on a target boardin which a variety of busesare led out and connected to a break board. The break boardis provided with a break condition storage sectionand a break signal generation section. Break conditions are written in the break condition storage sectionfrom the side of a debuggerthrough the debug circuit, the CPUand the various buses. Then, a user program stored in a ROMis executed. The break signal generation sectionmonitors signals on the various buses, and outputs a break generation signalwhen the signals on the various busescoincide with the break condition. The execution of the user program is interrupted (stopped) based on the break generation signal

Break board debugging device

The present invention provides a microcomputer that makes it possible to implement a real-time trace on a mass-produced chip using few terminals, acquire trace information from within a specified range, and measure execution times, together with electronic equipment and a debugging system comprising this microcomputer. A trace information output section () outputs trace information for implementing a real-time trace, to four dedicated terminals. It outputs instruction execution status information (DST[]) of the CPU to three terminals and the PC value (DPCO) of a branch destination when an PC absolute branch has occurred, serially to one terminal. A microcomputer () outputs information indicating the start and end of a trace range or execution-time measurement range to DST[] in a predetermined sequence. A debugging tool () determines the start and end of the trace range or execution-time measurement range from the values in DST[

The invention saves power by supplying minimum clocks required for respective blocks. In a clock control system that supplies clocks to a plurality of blocks, such as a CPU-, a bus, a peripheral circuit and other circuits, a clock supplied from a clock oscillator is supplied to clock control sections that are connected to the blocks, respectively. The clock is converted by the clock control sections into clocks with minimum clock numbers required to operate the blocks, respectively, and supplied to the blocks.

Clock control system using converting clock control sections to provide a minimum clock number to operate corresponding devices

An objective is to provide a microcomputer, electronic equipment and emulation method which can realize the optimum circumstance of evaluation while saving the number of terminals. An external bus is shared between external and emulation memories. In the emulation mode, the access of CPU to an internal ROM is switched to the access of CPU to the emulation memory through an external bus. The emulation mode is turned ON or OFF through a mode selection terminal or mode selection register. The emulation memory is controlled by a control signal CNT2 different from a control signal CNT1 which controls the external memory. A memory read signal in CNT2 become active at a timing earlier than that of a memory read signal in CNT1. Thus, the instruction is fetched and decoded within one clock cycle. A mode selection terminal is further provided for selecting a mode of performing the boot from the emulation memory, internal ROM or external memory and a made of selecting OPT mode.

Method for improving pin compatibility in microcomputer emulation equipment

An objective is to provide a microcomputer, electronic equipment and debugging system which can more effectively execute the debugging operation. A mini monitor section ( ) can perform data transfer between the mini monitor section and a main monitor section ( ). Based on the receive data, the mini monitor section ( ) performs debugging processing and also executes a jump command to an address at which an initializing program or a writing program for a flash memory ( ) is stored. Receive data (or primitive command) includes GO, write, read, external routine jump commands, and send data contains a flag for announcing an error in data writing. The main monitor section ( ) converts a debugging command into a primitive command. Receive data also contains a command identifying data. Both the program debugging and rewriting operations can be performed on a single host system ( ) in the present invention.

Growing community of inventors

Fujimi-machi, Japan

Makoto Kudo