Kabushiki Kaisha Toshiba

Toshiba Memory Corporation

Kioxia Corporation

Makoto Iwai

Hiroshi Nakamura

Yoshihisa Watanabe

Masaki Fujiu

Kazuhisa Kanazawa

Koichi Fukuda

Isao Sakai

Teruji Yamakawa

Rieko Tanaka

Koki Kanda

Hirsohi Nakamura

Hideaki Tsunashima

Akio Okazaki

A memory includes first and second select gate transistors, memory cells, a source line, a bit line, a selected word line which is connected to a selected memory cell as a target of a verify reading, a non-selected word line which is connected to a non-selected memory cell except the selected memory cell, a potential generating circuit for generating a selected read potential which is supplied to the selected word line, and generating a non-selected read potential larger than the selected read potential, which is supplied to the non-selected word line, and a control circuit which classifies a threshold voltage of the selected memory cell to one of three groups by verifying which area among three area which are isolated by two values does a cell current of the selected memory cell belong, when the selected read potential is a first value.

Nonvolatile semiconductor memory including a read operation

A semiconductor storage device of embodiments is a semiconductor storage device including a memory cell array including a plurality of non-volatile memory cells, a sequencer configured to control a sequence based on read operation of reading data from the memory cell array, and a column decoder, the sequencer controlling the sequence of changing a ready/busy signal from ready to busy after receiving a read command and an address signal, reading data from the memory cell array using a sense amplifier after changing the ready/busy signal to the busy, changing the ready/busy signal from the busy to the ready after storing data in the data latch circuit, receiving a data output command after changing the ready/busy signal to the ready, and, in a case where a first condition occurs, writing log data including the data stored in the data latch circuit in a memory area of the memory cell array.

Semiconductor storage device

A mobile storage device includes first and second memory regions in one or more semiconductor memory devices, a positioning system configured to generate positional information indicating a position of the mobile storage device, and a controller. The controller is configured to allow access to the first memory region and prohibit access to the second memory region when the positional information indicates that the position of the mobile storage device is within a first area, and prohibit access to the first memory region and allow access to the second memory region when the positional information indicates that the position of the memory storage device is within a second area, which is different from and does not overlap with the first area.

Data security management based on device locations and connection states

A memory system includes a semiconductor storage device that includes a plurality of blocks, and a controller configured to designate a block of the semiconductor storage device as a partial bad block if, after performing a write operation on the block, status information read from the semiconductor storage device indicates that the write operation failed, and read data that is returned when a read operation is performed on data written pursuant to the write operation has errors that are correctable. The controller is configured to manage a partial bad block differently from a bad block.

Memory system

Nonvolatile semiconductor memory and verify read operation

Nonvolatile semiconductor memory with dual latch sense amplifier

According to one embodiment, a nonvolatile semiconductor storage device includes a memory cell array where memory cells are arranged in a cell well in a row direction and a column direction in a matrix; word lines which select the memory cell in the row direction; bit lines which select the memory cell in the column direction; a sense amplifier which determines a value stored in the memory cell based on a potential of the bit line; a peripheral transistor in the memory cell array which is arranged in the periphery of the memory cell array; and an enhancement type transistor which drives a gate of the peripheral transistor.

Nonvolatile semiconductor storage device

A nonvolatile semiconductor memory device includes bit lines, word lines, NAND strings, source lines, first and second select gate transistors, and a controller. After giving a first potential to the second select gate transistors, the controller gives a second potential lower than the first potential to the second select gate transistors, gives a third potential to the memory cells which are insufficient in the writing, gives a fourth potential higher than the third potential to the memory cells which are just before completion of the writing, and gives a fifth potential higher than the fourth potential to the memory cells which are completed in the writing. The first potential is capable of turning on the second select gate transistors. The second potential is capable of turning off the second select gate transistors.

Nonvolatile semiconductor memory device

Nonvolatile semiconductor memory

Growing community of inventors

Yokohama, Japan

Makoto Iwai