Kabushiki Kaisha Toshiba

Makoto Ichida

Kazutaka Nogami

Hiroshi Sukegawa

Shigeru Tanaka

Takayasu Sakurai

Naohiro Matsukawa

Fumitoshi Hatori

Hiroshi Shimizu

Masanori Wada

Katsuhiko Sakimoto

Kazuma Tashiro

According to one embodiment, a memory system includes a nonvolatile semiconductor storage able to hold data, a temperature measurement section configured to measure the temperature of the semiconductor storage, a temperature varying section configured to change the temperature of the semiconductor storage, and a control circuit including a transmitter configured such that data received from a host is transferred to the semiconductor storage, and a temperature storage configured to store temperature information received from the temperature measurement section.

Memory system

According to one embodiment, there is provided a memory system including a bus master, a bus slave, and a memory device. The bus slave includes a synchronizing unit, and a speed-enhancing unit. The synchronizing unit is connected to a bus. The synchronizing unit receives the data in synchronism with a third clock. The third clock is in synchronous relation with a second clock and is slower than a first clock. The speed-enhancing unit enhances a transfer speed from a speed corresponding to the third clock to a speed corresponding to the second clock, by transferring the data received in the synchronizing unit to the memory device in synchronism with the second clock.

Memory system, memory controller, and synchronizing apparatus

Cells are formed on a substrate. First and second cell power wiring lines extend in a first direction on the substrate. First and second intermediate layer power wiring lines are formed on the first and second cell power lines. First upper layer power wiring lines are formed on the first and second intermediate layer power lines. The first upper layer power wiring lines extend in a second direction crossing the first direction at right angles. First contact members are formed between the first cell power lines and the first upper layer power lines. Second contact members are formed between the second cell power lines and the first upper layer power lines. The second contact members are arranged at positions shifted from a straight line which passes through the first contact members in the first direction and a straight line which passes through the first contact members in the second direction.

Semiconductor integrated circuit with improved power supply system

A method for processing data by utilizing hierarchial cache memories in a system where a lower cache is connected between a processor and a higher cache memory and the higher cache memory is in turn connected to a main memory or connected through a serial arrangement of higher cache memories to the main memory. When a cache miss occurs in the lower cache and the lower cache is full of 'dirty data', the data is not written to the main memory but instead to the higher cache. Dirty data is written into the main memory when at least all of the cache memories are filled with dirty data and a cache miss occurs.

Method for processing data by utilizing hierarchical cache memories and

A field programmable gate array comprises: a first wire group (8) composed of a plurality of first wires; a second wire group (7) composed of a plurality of second wires; switching sections (9) provided at least one intersection between the first and second wires of the first and second wire groups (8, 7), for determining connection and disconnection between both when programmed; and a basis cell (6B) having a first transmission gate (4) turned on in response to a high gate voltage and a second transmission gate (5) turned on in response to a low gate voltage, gates of the first and second transmission gates (4, 5) being connected to each other as a common gate or being connectable to each other as a common gate by the switching sections when programmed, input and output terminals and the common gates of the first and second transmission gates (4, 5) being connected to any of the first wires of the first wire group (8), respectively. Wiring of different lengths is provided for connecting circuit elements within the field programmable gate array, with wires of a first length being more numerous than wires of a second, longer length. The quantity of wires of different lengths varies in accordance with the -2.5 power of the length of the wires.

Growing community of inventors

Yokohama, Japan

Makoto Ichida