Samsung Electronics Co., Ltd.

Socionext Inc.

Osaka Gas Company Limited

Panasonic Corporation

Makoto Hirano

Akihiro Suzuki

Jinyoung Kim

Daisuke Fujiwara

Norihiko Mizobata

Masahiro Takeuchi

Hironori Kubo

Woojung Sun

Hitoshi Inoue

Hiroki Murakami

Yongsung Cho

Taehui Na

Bilal Ahmad Janjua

Yong-jun Lee

Jung Sunwoo

Junho Shin

YongSung Cho

Masao Kuriyama

Jun-Gyu Lee

Tomohisa Miyamoto

Yuichiro Nakagaki

Min-Hwi Kim

Chea-Ouk Lim

Kaiyun Cheng

Shinichi Marui

Ryo Sakaji

A memory device includes a memory cell array and a page buffer circuit, wherein the page buffer circuit includes page buffer units including upper page buffer units and lower page buffer units and cache units arranged between the upper page buffer unit and the lower page buffer units. The cache units include upper cache units and lower cache units. Each page buffer unit includes a sensing node and a pass transistor. The upper cache units share a first combined sensing node, and, the lower cache units share a second combined sensing node. In a data transmission period, sensing nodes respectively included the page buffer units are electrically connected to one another through serial connections of the pass transistors respectively included in the page buffer units.

Page buffer circuit and memory device including the same

A resistive memory device includes a first bit line group including a first edge bit line, a second bit line group including a second edge bit line, and a first boundary transistor configured to apply a non-selection voltage to the second edge bit line according to a selection of the first edge bit line. The first edge bit line of the first bit line group is disposed closest to the second bit line group, and the second edge bit line of the second bit line group is disposed closest to the first bit line group.

Resistive memory device with boundary and edge transistors coupled to edge bit lines

A three-dimensional (3D) memory device includes a memory cell array, a first sense amplifier and a second sense amplifier. The memory cell array includes lower memory cells respectively arranged in regions where lower word lines intersect with bit lines and upper memory cells respectively arranged in regions where upper word lines intersect with the bit lines. The first sense amplifier is connected to a first lower word line and performs a data sensing operation on a first lower memory cell connected between a first bit line and the first lower word line. The second sense amplifier is connected to a first upper word line and performs a data sensing operation on a first upper memory cell connected between the first bit line and the first upper word line. The data sensing operations of the first and second sense amplifiers are performed in parallel.

3D memory device

A nonvolatile memory device includes: a memory cell array in which a plurality of memory cells are arranged at intersections between a plurality of word-lines and a plurality of bit-lines; and a word-line select circuit configured to, in response to a first global word-line select signal, start reading a target memory cell connected to a target word-line and provide a reading result of the target memory cell to a sensing line through at least one adjacent word-line that is adjacent to and coupled to the target word-line.

Nonvolatile memory and method of operating nonvolatile memory

A read method of a nonvolatile memory device is provided. The method includes storing data sensed from selected memory cells of the nonvolatile memory device into a page buffer, performing an error decoding operation by performing error detection on the sensed data to detect and error, correcting the detected error if the error is detected, and overwriting the page buffer with the corrected data, and de-randomizing data stored in the page buffer by using a seed after the error decoding operation has completed.

Nonvolatile memory device and read and copy-back methods thereof

An HDMI source conversion device according to one aspect of the disclosure includes an HDMI interface, an IP interface, and a converter. The HDMI interface receives a first signal based on the HDMI communication protocol. The IP interface receives address information from a control device via a network based on the Internet protocol, the control device being connected to the network, and the address information indicating the address on the network of an HDMI sink conversion device that is a device different from the control device. The converter converts the first signal based on the HDMI communication protocol into a second signal based on the Internet protocol by adding at least the address information to the first signal received by the HDMI interface. The IP interface transmits the second signal to the HDMI sink conversion device via the network.

Data transfer system and conversion device

A memory device includes a memory cell array including memory cells disposed at points at which word lines and bit lines intersect, a first decoder circuit determining a selected bit line and non-selected bit lines among the bit lines, a second decoder circuit determining a selected word line and non-selected word lines among the word lines, a current compensation circuit providing a current path drawing a compensation current from the selected word line to compensate for off currents flowing in the non-selected bit lines, a first sense amplifier comparing a voltage of the selected word line with a reference voltage and outputting an enable signal, and a second sense amplifier outputting a voltage difference between the voltage of the selected word line and the reference voltage during an operating time determined by the enable signal in a readout operation mode of the memory device.

Memory device having an increased sensing margin

An integrated circuit memory device includes an array of resistive memory cells and a programming circuit, which is electrically coupled by a plurality of word lines and plurality of bit lines to corresponding rows and columns of the resistive memory cells. The programming circuit includes a control circuit and word line driver that are collectively configured to generate word line program voltages having magnitudes that vary as a function of the row and/or column addresses of the resistive memory cells in the array, during operations to program the array with write data. According to the function, the magnitude of a word line program voltage associated with a first resistive memory cell having a first parasitic resistance is less than a magnitude of a word line program voltage associated with a second resistive memory cell having a second parasitic resistance, which is greater than the first parasitic resistance.

Resistive memory devices having address-dependent parasitic resistance compensation during programming

A semiconductor integrated circuit operates with a voltage supplied from a first power supply IC to transmit and receive data to and from an external memory. The semiconductor integrated circuit includes: an interface circuit operating with a voltage supplied from a second power supply IC and accessing the external memory to transmit and receive data to and from the external memory; a determination circuit which determines, based on a result of the access by the interface circuit, an AC timing specification between the external memory and the interface circuit to generate control information for controlling an output voltage of the second power supply IC in accordance with the AC timing specification; and a voltage control circuit which controls the output voltage of the second power supply IC in accordance with the control information.

Method for controlling power supply voltage in semiconductor integrated circuit

A nonvolatile memory device includes a memory cell array including a plurality of first segments having a write data, and a plurality of second segments having a programmed information defining a programmed segment from the plurality of first segments. A randomizer is configured to randomize the write data. An error correction circuit is configured to perform an error correction operation on the write data. A control logic is configured to determine the programmed information from an address received from a memory controller, and to determine whether to operate the randomizer and the error correction circuit based on the determination of the programmed information during the program operation. A page buffer is configured to store the write data and the programmed information during the randomizing and the error correction operation.

Nonvolatile memory device for performing at least one of randomization operation and error correction operation

A method of reading a nonvolatile memory device including a plurality of pages coupled to a plurality of word lines and a plurality of bit lines, each of the plurality of pages including a data region storing a data and a flag region storing a flag, includes applying a first read voltage to a selected word line to generate first sensing data and a first sensing flag; applying a second read voltage to the selected word line to generate second sensing data and a second sensing flag, generating determination data by performing a logical operation on the first and second sensing data; determining a shift voltage based on the determination data and the read flag; and applying a third read voltage, based on the shift voltage, to the selected word line to generate a read data.

Growing community of inventors

Seongnam-si, South Korea

Makoto Hirano