Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Matsushita Electric Ind., Ltd.

Makoto Hirai

Tokuzo Kiyohara

Kosuke Yoshioka

Hideshi Nishida

Kozo Kimura

Hiroyuki Morishita

Hiroyuki Oka

Yoshiyuki Mochizuki

Takaharu Tanaka

Tsutomu Hashimoto

Toshiaki Tsuji

Tetsuji Mochida

Ryuji Matsuura

Kiyoshi Maenobu

Kenji Nishimura

Toshiya Naka

Yutaka Tanaka

Yoshiyuki Wada

Akio Nishimura

Tadashi Kobayashi

Akifumi Yamana

Yorihiko Wakayama

Nobutaka Kitajima

Toshiyuki Ochiai

Minobu Abe

Jiro Minehisa

Kazu Segawa

Atsushi Nishiyama

Yosuke Furukawa

Yukiharu Ieda

A 3D image processing apparatus includes: L and R graphic decoders which decode coded stream data to generate left-eye and right-eye image data; an image output control unit which outputs the generated image data; and a control unit which, when a decoding error occurs in generating one of the image data, and a successful decode occurs in generating the other of the image data, (i) shifts, by a preset offset, a pixel position of the other of the image data, to generate pseudo image data as the one of the image data, and (ii) outputs the pseudo image data to an image output control unit, wherein the image output control unit outputs the other of the image data and the pseudo image data, when the decoding error occurs in generating the one of the image data and the successful decode occurs in generating the other of the image data.

Three-dimensional image processing apparatus and method of controlling the same

The present invention provides an image decoding apparatus that realizes speed-up processing of taking out an MR (macroblock remainder) from a fixed length unit that consists of a first DCT block and the MR, without increasing cost. A Setup processoroutputs one out of a plurality of fixed length units that constitute an SB (synchronized block). First, calculation is performed for a length from a beginning of the fixed length unit to a EOB (end of block) that is included in the fixed length unit. The calculated length is then used as an offset in taking out the MR. Then an end portion of a second DCT block that is included in the MR is combined with a corresponding beginning portion of the second DCT block, in order to obtain the complete second DCT block. The complete second DCT block is outputted to a variable length code decoder

Image decoding apparatus, recording medium which computer can read from, and program which computer can read

A transcoder for resizing video data and outputting the resized video data to a reproduction apparatus. The reproduction apparatus reproduces the resized video data by repeating a display period and a non-display period alternately. The transcoder includes: a resizing unit that resizes the video data; and a control unit that causes the resizing unit to resize the video data to first video data having a first resolution so that the reproduction apparatus displays one image during each display period, and causes the resizing unit to resize, during each period between the resizing of the video data to the first video data, the video data to second video data having a second resolution that is lower than the first resolution.

Transcoder

A media processing apparatus is made up of an I/O processing unit for performing input/output processing which asynchronously occurs due to an external factor and a decode processing unit for performing decode processing mainly for decoding of data streams stored in a memory in parallel with the input/output processing. The input/output processing includes receiving the data streams which are asynchronously inputted, storing the inputted data streams in the memory, and supplying the data streams from the memory to the decode processing unit. The decode processing unit is made up of a sequential processing unit mainly performing condition judgements on the data streams and a routine processing unit performing decode processing on compressed video data aside from header analysis of the compressed video data in parallel with the sequential processing. Accordingly, the input/output processing means and the decode processing means are respectively charged with the asynchronous processing and the decode processing, and the input/output processing means and the decode processing means operate in parallel as in pipeline processing. As a result, the decode processing means can be devoted to the decode processing, regardless of asynchronous processing. Accordingly, processes including input processing of stream data, decode processing of the inputted data, and output processing of decoded data are executed efficiently.

Media processing apparatus which operates at high efficiency

A pixel calculating device that performs vertical filtering on pixel data in order to reduce frame data in a vertical direction. The pixel calculating device includes a decoding unit for decoding compressed video data to produce frame data, frame memory for storing the frame data, a filtering unit for reducing the frame data in a vertical direction by the vertical filtering to produce a reduced image, buffer memory for storing the reduced image outputted from filtering unit , and a control unit for controlling filtering unit based on a decoding state of the video data by decoding unit and a filtering state of the frame data by filtering unit , so that overrun and underrun do not occur in filtering unit

Pixel calculating device

A pixel calculating device for performing vertical filtering that includes 16 pixel processing units 1 to 16 and an input buffer group storing 16 pieces of pixel data and filter coefficients. Each of the pixel processing units performs operations using the pixel data and a filter coefficient supplied from input buffer group , and then acquires pixel data from an adjacent pixel processing unit. Further operations are performed by each of the pixel processing units using the acquired pixel data and operation results are accumulated. Filtering is carried out through a repetition of this acquiring and accumulation process, the number of taps being determined by the number of repetitions.

The counter is set with an initial value of &ldquo;1&rdquo; and is a counter with a maximum value of &ldquo;4&rdquo;. This counter increments the count value held by the flip-flop in synchronization with a clock signal so that the count value changes as shown by the progression 1,2,3,4,1,2,3,4. This clock signal is also used by the instruction decode control unit to control the execution of instructions, with the counting by the counter being performed once for each instruction execution performed by the instruction decode control unit . The comparator compares the count value counted by the counter with the maximum value &ldquo;4&rdquo;, and when the values match, sets the task switching signal chg_task_ex at a &ldquo;High&rdquo; value, so that the processing switches to the execution of the next task.

Processor capable of efficiently executing many asynchronous event tasks

When an OSD data storage area for storing OSD data needs to be reserved, an area of a frame storage apparatus that should store macroblocks corresponding to an invisible area on a screen is allocated as the OSD data storage area. There is no degradation in picture quality. When doing so, the data reduction control unit receives an instruction to reserve the OSD data storage area and discards the corresponding macroblocks. The OSD data access unit writes the OSD data into an area of the frame storage apparatus that was assigned to store the discarded macroblocks.

IMAGE DECODING APPARATUS THAT PERFORMS IMAGE DECODING SO THAT FRAME AREAS THAT OCCUPY A LARGE AREA IN A STORAGE APPARATUS CAN BE USED FOR OTHER PURPOSES, AND A RECORDING MEDIUM RECORDING AN IMAGE DECODING PROGRAM

Memory control unit and memory control method and medium containing program for realizing the same

Bitstream analyzing unit,fetches a coded block pattern and a coded quantized DCT coefficient from each block in a bitstream. Entropy decoding unit,decodes the coded block pattern into a block pattern and decodes the coded quantized DCT coefficient into pairs of a run length and an effectiveness factor. Dequantization unit,generates orthogonal transformation coefficients from the pairs of a run length and an effectiveness factor. Inverse Discrete Cosine Transform (IDCT) unit,generates a difference image from the orthogonal transformation coefficients. Decode controlling unit,instructs first selecting unit,to select constants &ldquo;0&rdquo;output from first constant generating unit,when the image is a &ldquo;skipped&rdquo; block. Image storage unit,stores a plurality of reference frame pictures having been decoded. Image restoring unit,restores an original block by adding a decoded difference image to a reference block read from the reference frame pictures stored in the image storage unit

Image decoding apparatus

Image decoder and image memory overcoming various kinds of delaying

An apparatus of the invention generates an image including a plurality of pixels by mapping a plurality of texture data onto a surface of an object. The apparatus includes: a geometrical transformation section for geometrically transforming a curved surface defined in a 3-dimensional space into a curved surface in a 2-dimensional screen space; a micro-polygon generating section for dividing the curved surface in the 2-dimensional screen space into a plurality of partial curved surfaces in accordance with the number of the plurality of texture data, and for generating a micro-polygon in accordance with each of the plurality of partial curved surfaces; an area contribution determining section for determining an area contribution of the micro-polygon to a pixel included in the image, based on a relative positional relationship between the micro-polygon and the pixel; a texture data acquiring section for acquiring texture data in accordance with the micro-polygon; and an intensity-value determining section for determining an intensity value of the pixel, based on the area contribution determined by the area contribution determining section and the texture data acquired by the texture data acquiring section.

Apparatus and method for generating an image for 3-dimensional computer

The rendering apparatus of this invention includes: means for determining a pixel including a depicting point on a polygon, the polygon being projected to a plane having a plurality of pixels; and means for performing a rendering calculation based on a sample point which has a fixed position with respect to the pixel, and for outputting a calculating result.

Rendering apparatus and rendering method, and mapping apparatus and

An apparatus for parallel image generation has four geometric data buffers for storing four partial geometric data, respectively, and four image generators connected respectively to the four geometric data buffers. Each image generator generates a partial image data for every pixel in a frame. Further provided are four image mergers connected respectively to the four image generators. The four image mergers are also connected in series. An initial image generator for generating a background image is connected to the first image merger for merging the background image data and the partial image data from the first image generator. Each of the second to fourth image merger merges an output merged data from the previous image merger and the partial image data from the corresponding image generator. A timing control is connected to the four image mergers for controlling the merging timing in such a manner that the image merger carries out the merging operation of a pixel after the previous image merger has carried out the merging operation of the same pixel.

Growing community of inventors

Suita, Japan

Makoto Hirai