Kabushiki Kaisha Toshiba

Tokyo Shibaura Denki Kabushiki Kaisha

Makoto Hideshima

Wataru Takahashi

Tetsujiro Tsunoda

Keizo Tani

Chihiro Okado

Masaru Ando

Yutaka Tomisawa

Shinjiro Kojima

Masashi Kuwahara

Kenichi Muramoto

Shingo Yanagida

Masahi Kuwahara

Ken-ichi Muramoto

Shuzo Saeki

An overcurrent protection circuit for a power transistor for generating a main current in response to a gate drive voltage generated by a gate circuit. The overcurrent protection circuit includes a current detection circuit for detecting the main current flowing in the power transistor to generate a detection voltage corresponding to the main current, and a level detection circuit connected to receive the detection voltage for generating a control current corresponding to a difference between the detection voltage and a prescribed value when the detection voltage exceeds the prescribed value. The overcurrent protection circuit further includes a current control circuit connected to receive the control current for limiting the main current by regulating the gate drive voltage based on the control current, and a drive instruction control circuit connected to receive the control current for making the main current zero by controlling the gate drive voltage to an OFF condition based on the control current.

Power transistor overcurrent protection circuit

One of a pair of the module type semiconductor devices, signal input terminals are located on the other side of current output terminals with respect to current input terminals, and that, in the other of a pair of the module type semiconductor devices, signal input terminals are mounted on the other side of current input terminals with respect to current output terminals. Distance of connections between element in the case of bridge connections may be shortened to the minimum. Since the signal input terminals may be located outside the bus bars, openings need not be made in the bus bar. Space or the bus bar's surface area may be effectively used, with the result that a decrease in commutating inductance is achieved.

Module-type semiconductor device of high power capacity

A semiconductor element is formed in a semiconductor substrate. An electrode wiring pattern which is connected to the active region and contains aluminum as the main component is formed on the main surface of said semiconductor substrate. A metal bump is formed on the electrode wiring pattern. The metal bump contains zinc of 1 to 10% in mass percentage in addition to at least one element selected from a group consisting of tin, lead and aluminum a second metal bump is formed having a lower melting point than that of first bump. The second bump contains lead, tin and at least one of silver and copper.

Metal bump type semiconductor device and method for manufacturing the

A semiconductor device includes a metallic electrode formed on a semiconductor substrate, and a metallic terminal formed on a metal base through an insulating material, in parallel to the metal electrode. A metallic wire electrically connects the metallic electrode to the metallic terminal. In a metallic conductor having a current capacity larger than that of the metallic wire, one end is in contact with the metallic terminal, and the other end is in contact with the metallic electrode.

Semiconductor device including a metallic conductor for preventing

A conductivity modulation type semiconductor device comprises a semiconductor anode substrate of a P type having two surfaces, a semiconductor substrate of an N type having two surfaces, the semiconductor substrate having a high impurity layer-like region on one surface thereof and a low concentration drain region on the other surface thereof, a body region of P type formed in the drain region and exposed at one surface of the semiconductor substrate, source regions of an N type formed in the body region and exposed at the other surface of the semiconductor substrate, and a gate layer formed within the isulating layer, which extends between the source and drain regions, on the body region. The other surface of the anode substrate is polished and is intimately joined to the polished surface of the semiconductor substrate to form a junction layer therebetween.

Conductivity modulation type semiconductor device and method for

In a power semiconductor device such as an IGBT, a fifth region of n conductivity type is provided. The fifth region is formed in a portion of a second region (drain region) contacting an insulating layer below the gate layer. The fifth region contacts a third region (base region) and has an impurity concentration higher than that of the second region. Therefore, even when a carrier life time is sufficiently short, an electron distribution density can be kept high in the entire fifth region and the second region under the third region (base region) near the fifth region, and the localization of a hole current is moderated (in a case of a p-type base and an n-type drain). As a result, a maximum controllable current is increased, and a wide safe operation area can be obtained.

Insulated gate bipolar transistor with a shortened carrier lifetime

A high withstand voltage Darlington transistor circuit is comprised of a Darlington transistor and a bypass circuit. This bypass circuit is comprised of a bypass transistor whose collector is connected to the base of an earlier stage transistor of the transistors which make up the Darlington transistor and whose emitter is connected to the base of a later stage transistor. The base of the bypass transistor is connected to the collector of the Darlington transistor via a diode and the resistor. When the collector-emitter voltage of the Darlington transistor crosses a specified value, the bypass transistor operates and a base current of the Darlington transistor is supplied to the base of the later stage transistor without being supplied to the earlier stage transistor. The result is that the current amplification ratio of the Darlington transistor is substantially decreased, and the withstand voltage is substantially increased.

High withstand voltage Darlington transistor circuit

A semiconductor device with a planar p-n junction and a guard ring region, wherein an oxide film is covered on the surface between the p-n junction and the guard ring, and a glass film is formed on the surface surrounding the guard ring region.

Semiconductor device with glass layer contacting outer periphery of

A junction type semiconductor device, wherein a protective diode is formed in a part of the region consisting of a base region and a collector region. The device permits reducing the manufacturing cost of semiconductor elements, makes it possible to provide a smaller electric apparatus, and is high in reliability.

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Tokyo, Japan

Makoto Hideshima