Fujitsu Corporation

Fujitsu Semiconductor Limited

Makoto Hamaminato

Naoto Adachi

Hiromasa Yamauchi

Teruhisa Ninomiya

Shoichiro Kawashima

Akihiro Wada

Toshihiko Mori

Tatsuya Kikuzuki

Kaoru Yokoo

Mitsuru Tomono

Kensuke Sawada

Naoto Yoneda

Shiho Nakahara

Ryuhei Sasagawa

An information processing apparatus includes a memory, and a processor coupled to the memory and configured to obtain location information indicating locations of a wireless transmitter and a wireless receiver, simulate a first power of a first reception signal at the wireless receiver in a condition that a radio signal is transmitted from the wireless transmitter, identify a first probability distribution model in accordance with the first reception signal, identify a first parameter of the first probability distribution model in accordance with the first power and a propagation environment defined by the locations of the wireless transmitter and the wireless receiver indicated by the location information, and based on the first probability distribution model using the first parameter, simulate a second power of a second reception signal at around the wireless receiver.

Information processing apparatus, method and non-transitory computer-readable storage medium

There is provided a radio wave interference analysis apparatus configured to analyze a state of interference due to a plurality of interference signals of a plurality of interference sources on a target signal of a wireless device as an evaluation target at a reception point, the radio wave interference analysis apparatus including a memory, and a processor coupled to the memory and the processor configured to calculate a first probability of failure of reception of the target signal at the reception point due to collision of the target signal with an interference signal of the plurality of interference signals, calculate a second probability of failure of reception of the target signal at the reception point due to the interference signal of the plurality of interference sources, and output the first probability and the second probability.

Radio wave interference analysis apparatus, method, and medium

To provide a receiving device and a receiving method which achieve iterative decoding regarding concatenated codes containing a convolutional code while suppressing increase in circuit scale, a decoder and an error correcting part iteratively perform decoding and error correction corresponding to a convolutional code on soft-decision inputs corresponding to the received signal sequence. Depending on whether a decoding result matches error corrected decoded data obtained in previous processing or not, penalties are calculated corresponding to branches transiting with the respective decoded results, and a branch metric is calculated by reflecting the calculated penalties as to decrease likelihood ratio of each of the branches to which the penalties are to be added. The obtained branch metric is input to a decoder, thereby reflecting the penalty corresponding to the decoding result.

Receiving device and receiving method

A digital broadcast demodulator receives a tuner signal output from a tuner and carries out demodulation processing on the tuner signal by using an internal clock signal that is synchronized with a reference signal. The digital broadcast demodulator has an internal clock-signal generator and an internal clock frequency controller. The internal clock-signal generator generates the internal clock signal, and the internal clock frequency controller controls a frequency of the internal clock signal in accordance with a reception channel.

Digital broadcast demodulator and digital broadcast demodulation method for suppressing degradation of reception characteristics

An OFDM signal is demodulated to generate a frequency domain signal in each of a plurality of branches. A diversity combining unit combines the demodulated signals respectively obtained in each of the branches. A clock recovery unit recovers the clock for the OFDM signal. A guard correlation unit detects the phase error of the OFDM signal. A decision unit identifies a branch having high reliability. A clock error correction unit generates a correction instruction, in accordance with the average value of the phase errors in the branch having high reliability. The clock recovery unit in each of the branches respectively corrects the error of the clock in accordance with the correction instruction.

OFDM receiving apparatus having plurality of OFDM branches

A receiver circuit in each branch has an FFT unit that performs Fourier transform on OFDM signals. A slave branch FFT window control unit determines whether an undesired wave is a preceding wave or a delay wave, and notifies a master branch of the result. In response to the notification from the slave branch, a master branch FFT window control unit controls a position of an FFT window that indicates a time range in which Fourier transform is performed on OFDM signals.

OFDM receiver apparatus having a plurality of receiver circuits and OFDM receiving method

A semiconductor memory device which can reduce a power consumption by reducing a charging and discharging current for a gate capacity of a transistor used for pulling up a bit line which constitutes a write recovery circuit. A pair of first and second bit lines are connected to a memory cell. A potential of one of the first and second bit lines is decreased during a write cycle in accordance with write data. A first loading element is connected between a power source line and the first bit line. The power source line supplies a positive power source voltage. A second loading element is connected between the power source line and the second bit line. A first transistor is provided for pulling up the first bit line. The first transistor has a current input terminal connected to the power source line and a current output terminal connected to the first bit line. A second transistor is provided for pulling up the second bit line. The second transistor has a current input terminal connected to the power source line and a current output terminal connected to the second bit line. A transistor drive circuit drives, during a write recovery period, one of the first transistor and the second transistor which is connected to one of the first bit line and the second bit line which is set to a lower potential.

Semiconductor memory device and a semiconductor integrated circuit

A semiconductor memory device includes cells arranged in a matrix formation. Each of the cells includes a driver transistor, a read transistor which is controlled by a read word line and outputs read data read from the cell to a read bit line, a write transistor which is controlled by a write word line and supplies write data supplied from a write bit line to a cell capacitor connected to a gate of the driver transistor, and a column write select transistor which is controlled by a column write select signal line and is connected to the write transistor in series. The write data is supplied to the cell capacitor via both the column write select transistor and the write transistor.

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Kawasaki, Japan

Makoto Hamaminato