Kabushiki Kaisha Toshiba

Fuji Xerox Co., Ltd.

Fujifilm Business Innovation Corp.

Makoto Hamada

Hiroshi Maejima

Masahiro Yoshihara

Kazuyoshi Muraoka

Tomokazu Yoshimura

Hisashi Shirakawa

Takumi Abe

An information processing apparatus includes a processor configured to: store document information of a document in a predetermined storage region when processing that does not include a storing process of the document is executed on the document; display the document information stored in the predetermined storage region on a display when executing processing, the document information including at least one item of the document information, and cause a user to select an item of the document information from the at least one item of the document information; and execute processing by using the selected item of the document information.

Information processing apparatus and method and non-transitory computer readable medium

An information processing apparatus includes a management unit that deletes from a first region a fax document that has been successfully transferred to a predetermined transmission destination and moves from the first region to a second region a fax document that has been unsuccessfully transferred to a transmission destination. A user is not permitted to perform an operation on the fax document stored in the first region and the user is permitted to perform an operation on the fax document stored in the second region.

Information processing apparatus for retransferring fax documents that were unsuccessfully transmitted

An information processing apparatus includes a display and a processing execution unit. The display displays an operator for receiving an instruction to execute predetermined processing. At least part of information concerning the predetermined processing is not appended to the operator. When the operator is selected by a user, the processing execution unit starts to display associated information associated with the operator, continues to display the associated information for a predetermined time, and then executes the predetermined processing.

Information processing apparatus, image processing apparatus, and non-transitory computer readable medium

Provided is an image reading apparatus including an image reading section that reads an image formed on a recording medium to generate image data, a display section that displays plural selection images that are registered in advance, used in selection of a storage destination of the generated image data, and an identifying section that identifies a user who stores the image data, wherein the display section displays, when the user is identified by the identifying section, the selection image corresponding to the identified user, and reduces a number of the selection images to be displayed to be less than a number of all the plural selection images to display the selection image.

Image reading apparatus, display apparatus, non-transitory computer readable recording medium, and image displaying method

An image forming system includes a transmitter apparatus that transmits, to a predetermined storage location of multiple storage locations, identification information identifying a user and image data associated with the identification information, and multiple image forming apparatuses. Each of the image forming apparatuses includes a first storage unit that stores storage information indicating the storage locations, a storage location that is included in the storage locations and stores the identification information and the image data associated with the identification information, a retrieval unit that accesses the storage locations, indicated by the storage information stored on the first storage unit, when the identification information is inputted by the user, and retrieves the image data from the storage location, and an image forming unit that forms an image corresponding to the image data retrieved by the retrieval unit.

Image forming system with authentication unit, image forming apparatus, and computer readable medium

Image forming system including a plurality of image forming apparatuses, each storing information indicating a plurality of storage locations

According to one embodiment, a semiconductor storage device includes a memory cell array, a data latch group. The memory cell array comprises a plurality of memory cells. The data latch group holds a first address or a second address of the memory cell and data. The data latch group comprises a first data latch unit and a second data latch unit, the first data latch unit holds write data to be written to any of the memory cells or read data read from the memory cell array and the first address or the second address, while the second data latch unit holds second write data or read data.

Semiconductor storage device, host controlling the same, and memory system including the semiconductor storage device and the host

According to one embodiment, a semiconductor storage device includes first cells, first bit and first word, and first sense. The first cells are capable of holding 2-level or higher-level data. The first bit and first word are capable of selecting the first cells. The first sense detects a first current. The first sense includes a first supply unit, a first accumulation unit, a detector, and a counter. The first supply unit supplies a second current when the data is read. The first accumulation unit accumulates an amount of charge. The detector detects the potential the amount of charge. The counter counts output from the detector. The counter includes a second supply unit, a second accumulation unit, and a sensing unit. The second supply unit charges a first node. The second accumulation unit accumulates a charge. The sensing unit detects the amount of charge of the second accumulation unit.

Semiconductor storage device including memory cells capable of holding data

A nonvolatile semiconductor memory device capable of reading and verifying a negative threshold cell by biasing a source line and a well line to a positive voltage. The nonvolatile semiconductor memory device includes a precharge circuit which precharges a bit line to the same voltage as that of the source line in reading and verifying the negative threshold cell.

Nonvolatile semiconductor memory device

A semiconductor memory device includes memory cells, a source line, a word line, a bit line, and a driver circuit. The memory cells are formed on a semiconductor layer and have a charge accumulation layer and a control gate on the charge accumulation layer. The word line is connected to gate of the memory cell. The bit line is electrically connected to a drain of the memory cell. The source line is electrically connected to a source of the memory cell. The driver circuit varies potential of the semiconductor layer in conjunction with potential of the source line.

Semiconductor memory device which includes memory cell having charge accumulation layer and control gate

A semiconductor memory device includes a memory cell unit, word lines, a driver circuit, and a voltage generator. In the memory cell unit, memory cells having a charge accumulation layer and a control gate are connected in series. The word lines are connected to the control gates. The driver circuit selects the word lines. The voltage generator generates a first voltage and a second voltage lower than the first voltage. The first voltage is used by the first driver circuit to transfer a voltage to the unselected word line. The second voltage is used by circuits other than the first driver circuit.

A semiconductor memory device includes a memory cell array, a first row decoder which drives the memory cell array, and a second row decoder which drives the memory cell array. The first and second row decoders simultaneously drive the memory cell array.

Semiconductor memory device in which word lines are driven from either side of memory cell array

A nonvolatile semiconductor memory device includes a memory cell array having a plurality of word lines and a plurality of bit lines, and at least first and second page buffers to which the plurality of bit lines are connected. The plurality of word lines are divided into first and second word lines and the first and second word lines are arranged in positions corresponding to the at least first and second page buffers.

A semiconductor memory device includes a memory cell unit, word lines, a driver circuit, and a voltage generator. The memory cell unit includes a plurality of memory cells connected in series. Each of the memory cells includes a charge accumulation layer and a control gate. The word lines are connected to the control gate. The driver circuit selects one of the word lines and applies voltages to a selected word line and unselected word lines. The voltage generator includes first and second charge pump circuits and outputs a voltage generated by the first and second charge pump circuits to the driver circuit. The first charge pump circuit is exclusively used to generate a voltage for a first word line. The first word line is one of the unselected word lines located adjacent to the selected word line.

Growing community of inventors

Mountain View, CA, United States of America

Makoto Hamada