Renesas Technology Corp.

Makoto Dei

Yasuhiro Fujii

Yoshiyuki Ishigaki

Motoi Ashida

Takashi Terada

Yukio Maki

Tsuyoshi Koga

Tomohiro Hosokawa

Yasuichi Masuda

A semiconductor memory device having as its main storage portion a capacitor storing charges as binary information and an access transistor controlling input/output of the charges to/from the capacitor, and eliminating the need for refresh, is obtained. The semiconductor memory device includes a capacitor with a storage node located above a semiconductor substrate and holding the charges corresponding to a logical level of stored binary information, an access transistor located on the semiconductor substrate surface and controlling input/output of the charges accumulated in the capacitor, and a latch circuit located on the semiconductor substrate and maintaining a potential of the capacitor storage node. At least one of circuit elements constituting the latch circuit is located above the access transistor.

Semiconductor memory device

A memory cell of a static type semiconductor memory device includes a gate electrode of an MOS transistor formed on a main surface of semiconductor substrate via an insulator film, an interlayer insulator film covering the gate electrode, a set of contact holes provided in the interlayer insulator film and reaching a source and a drain located on either side of the gate electrode, a plug portion formed within each contact hole, and a metal interconnection formed on each plug portion. A space between contact holes located in the interlayer insulator film is made smaller than a space between contact holes on a surface of the interlayer insulator film.

Static type semiconductor memory device

Growing community of inventors

Hyogo, Japan

Makoto Dei