Other

Hitachi, Ltd.

Hitachi Video and Information System, Inc.

Makoto Asari

Akira Fujibayashi

Kazuhisa Fujimoto

Hiroki Kanai

Nobuyuki Minowa

Atsushi Tanaka

Hikari Mikami

Takahiro Sunada

Noritaka Narita

Naoto Kawakubo

The disk array controller includes a plurality of interfaces with respective processors for connecting with a host computer or disk devices, duplicated shared memories connected in a one to one ratio between each interface and respective access paths, a selector connected to the plurality of interfaces, and a cache memory connected to the selector. The number of access paths between the selector and the plurality of interfaces is greater than the number of access paths between the cache memory and the selector. Each processor performs dual writing in the duplicated shared memories.

Disk array controller including a plurality of access paths

Duplicated shared memory controller for disk array

An information recording method and apparatus records information signals having data signals and synchronizing signal patterns inserted at predetermined intervals of the data signals on a recording medium with a binary level by using a coding rule without a DC free property. The synchronizing signal patterns are inserted into the data at intervals of a fixed block length and are supplied to a recording apparatus as a mark/space pattern (record signal pattern). The data are converted into the same pattern as the mark/space pattern and an accumulated value (corresponding to the average DC value) for each block length is counted. The sum and the difference of an output of a memory which stores the accumulated values from the head of the sector to the (N-1)-st block, and the accumulated value of the N-th block, are compared with each other in absolute value. When the difference is smaller than the sum, a pattern inversion circuit is operated at the head of the N-th block of the record code string to invert the polarity of the record signal pattern, and when the sum is smaller than the difference, the pattern inversion circuit is not operated and the polarity of the record signal pattern is not inverted.

Information recording and reproducing apparatus for reducing average DC

Growing community of inventors

Yokohama, Japan

Makoto Asari