Pioneer Electronic Corporation

Pioneer Video Corporation

Pioneer Electric Corporation

Makio Yamaki

Hiroyuki Ishihara

Kazuo Watanabe

Yukio Matsumoto

Kazunaga Ida

Kazuhiro Hayashi

Toshiyuki Naoe

Shuhei Sudo

Soichi Toyama

Tatsushi Iizuka

Norimichi Katsumura

Hideyuki Terauchi

A coefficient data transfer processing method for a digital signal processor which has a coefficient address pointer independent of a program counter, whereby a processing program and coefficient data are transferred and supplied from a microcomputer determination, whether an instruction is a read instruction of the coefficient data to execute a read cycle steal or with is made; a value of a program counter with is made; when it is the read instruction, new coefficient data is transferred from the microcomputer to a transfer buffer at an instruction read stage and instruction decode stage in a processing unit; and the coefficient data stored in the transfer buffer is written into a coefficient data memory by the read cycle steal at an execute stage in the same processing unit.

Efficient data processing method for coefficient data in a digital

A digital signal processor (DSP) comprises a condition flag register directly accessible by the control microcomputer. Referring to a condition flag of the condition flag register every sampling period of the DSP, the DSP can change the content of a process every sampling period in accordance with the set status of the condition flag. The DSP sets the condition flag in the condition flag register at the beginning of a sampling period of the DSP by a set instruction, and resets the condition flag at the end of a sampling period by a reset instruction. The DSP may be modified to automatically reset the condition flag at the end of the sampling period in which the condition flag has been set.

Digital signal processor with selective sound operation

A digital signal processor (DSP) computes logarithmic values for data values of the input signal by using an approximation formula expanded into power series. To reduce the number of computing steps, the processor includes a shift circuit for shifting an input data value into a predetermined range of numeric values, a high-order coefficient memory for storing coefficient values of high order coefficients other than a zero-order coefficient of the approximation formula for data values within the predetermined range of numeric values, a zero-order coefficient memory for storing a coefficient value of the zero-order coefficient shifted according to the number of digits shifted by the shift circuit, and an address specifying circuit for specifying a reading address of the zero-order memory corresponding to the number of digit shifted by the shifted circuit. Also, a DSP computes an inverse logarithmic value of a data value of the input signal by using an approximation formula expanded into power series. The processor includes a summing circuit for summing a specific value to an input data value so that a summed value falls within a predetermined range of numeric values, a coefficient memory for storing coefficient values of the approximation formula for data values within the predetermined range of numeric values, and a shift circuit for shifting a result of computation performed by using the approximation formula by a number of digits corresponding to the specific value summed by the summing circuit.

Digital signal processor using a coefficient value corrected according

A digital signal processing device for outputting a holding data in an output register from a DSP in synchronism with a second clock pulse having a frequency lower than that of a first clock pulse for conducting arithmetic processing in the DSP. Accordingly, data to be output from the DSP can be directly read by a microcomputer, and contents in a coefficient memory and a delay time memory, for example, can be updated in accordance with the read data. Further, the digital signal processing device can be applied to an audio apparatus such as a loudness controller and a spectrum indicating apparatus.

Digital signal processing device and audio apparatus using the same

An audio signal data processing system comprises input device for sequentially supplying an audio signal data, data memory control device for writing the audio signal data into a data memory and reading-out the data from the data memory, delay memory control device for sequentially reading-out the audio signal data from the data memory and storing the data into a location of a delay memory indicated by a writing address and for reading-out the audio signal data from a location of the delay memory indicated by a reading address and writing the data into the data memory, address designating devices for designating the writing and reading addresses, arithmetic device for multiplying a predetermined coefficient data to the audio signal data having been read-out by the delay memory control device and written into the data memory, and output device for providing the audio signal data in accordance with a result of operation by the arithmetic device. The data memory control device and the delay memory control device write and read the audio signal data into and from the data memory through data buses independent from each other.

Audio signal processing system having independent and distinct data

There is provided a digital signal processor having first and second arithmetic operating sections each having a digital multiplier for multiplying values of two digital signal data and a digital accumulator for accumulating an output value of the multiplier, wherein an output of the multiplier in the second arithmetic operating section is connected to one input of the digital signal data of the multiplier in the first arithmetic operating section. There is also provided a digital signal processor in which the output of the multiplier in the second arithmetic operating section is connected to one input of each of both of the multipliers in the first and second arithmetic operating sections, respectively. Thus, the processing time can be reduced in the case of an arithmetic operation such that a plurality of coefficients are multiplied to a signal data value or an approximate value calculation.

Accelerated digital signal processor

A digital signal processor (DSP) makes a conditional judgment based on a value held in a flag register in accordance with the result of an arithmetic operation, selectively outputs data representing either a predetermined value or '0' in accordance with the result of the decision, adds the value of the output data to a value held in a coefficient memory address register, and holds the resultant value in the address register. Accordingly, in executing pipeline processing, a read address of the coefficient data memory can be directly designated without altering the flow of a program, thus shortening the processing speed and facilitating the programming.

Digital signal processor with improved pipeline processing

An audio signal data processing system includes first and second processing devices for processing audio signal data, the first and second processing device having input and output ports of at least two channels, and a control device for controlling the operation of the first and second processing device. The input audio signal data is supplied to the input port of one channel of each of the first and second processing devices, and output data from the output port of said one channel of said first processing device is supplied to the input port of the other channel of the second processing device, and output audio signl data are obtained at each output port of both channels of the second processing device. With this arrangement, one of the cascade processing and the parallel processing can be selectively performed without using a change-over switch provided outside the system.

Audio signal data processing system

An audio signal data processing system comprises an input device sequentially supplying incoming audio signal data, a data memory control device writing and reading-out the audio signal data into and from a data memory, a delay memory control device sequentially reading-out the audio signal data from the data memory and storing the data into a delay memory and sequentially reading-out the audio signal data from the delay memory and writing the data into the data memory, an arithmetic device multiplying predetermined coefficient data by the audio signal data having been read-out by the delay memory control device and written into the data memory and summing up results of the multiplication. The arithmetic device includes a plurality of multiplication and summing devices multiplying coefficient data by the audio signal data for each of data groups which are obtained by grouping a predetermined number of the audio signal data read-out by the reading device sequentially in the order of reading and subsequently summing up the multiplied values, and a filter device for executing a filter characteristic operation for calculated values respectively obtained by each of the multiplying and summing device, wherein a filter characteristic of the filtering device is made adjustable.

Growing community of inventors

Tokyo, Japan

Makio Yamaki