Hitachi, Ltd.

Makio Uchida

Yasuhiro Shinkai

Toshihiro Okabe

Michio Asano

Ayako Kumasaka

Jun'ichi Hirota

A photovoltaic power generation system includes a plurality of power generation panels and a power conditioner. The power generation panels and a radiation source are placed in a solar cell storage room buried typically in the ground. The radiation source includes radioactive waste generated in reprocessing of spent nuclear fuel. Each power generation panel has a phosphor member and a moderator member, which are disposed in that order on solar cells placed on a board. Radiation (for example, a gamma ray) emitted from the radiation source is injected on the power generation panel and is moderated by the moderator member. When the gamma ray with the reduced energy (below 100 keV) is injected on the phosphor member, it emits visible light. When the visible light is injected on the solar cells, electric power is generated.

Electric power generation method using solar cells and photovoltaic power generation system

A memory array is divided into a plurality of circuit blocks which each include wirings composed of electrically conductive polycrystalline silicon layers and circuit elements that will be operated by signals supplied via the wirings. Each circuit block is served with a signal via an aluminum layer. The signal supplied to the circuit block is transmitted to the circuit elements via an internal wiring. If the aluminum layer is broken, the circuit blocks formed on the remote side beyond the broken portion fail to work properly. Therefore, breakage of the aluminum layer can be easily detected. Further, since signals are supplied to the circuit blocks via an aluminum layer, the memory array operates at increased speeds.

Semiconductor integrated circuit device

A clock drive circuit device including clock drive circuits, each of which outputs a clock signal according to a predetermined logic function corresponding to the potential of condition signals, a circuit portion for executing the logic function which is composed of FETs, and has at least one FET for adjusting the FET configuration so that the number of FETs connected in series between a clock output terminal and a power source terminal as well as a ground terminal have predetermined values, respectively.

Clock drive circuit

A memory array is divided into a plurality of circuit blocks which each include wirings composed of electrically conductive polycrystalline silicon layers and circuit elements that will be operated by signals supplied via the wirings. Each circuit block is served with a signal via an aluminum layer. The signal supplied to the circuit block is transmitted to the circuit elements via an internal wiring. If the aluminum layer is broken the circuit block formed on the remote side beyond the broken portion fail to work properly. Therefore, breakage of the aluminum layer can be easily detected. Further, since signals are supplied to the circuit blocks via an aluminum layer, the memory array operates at increased speeds.

A semiconductor integrated circuit device having a semiconductor memory wherein part of the operation of a half precharge circuit is stopped by a reset signal, complementary data lines are set to high and low levels and a plurality of word lines are simultaneously brought into a selection state in order to effect a reset operation at a high speed.

Growing community of inventors

Fuchu, Japan

Makio Uchida