Nippondenso Co., Ltd.

Denso Corporation

Kabushiki Kaisha Toyota Chuo Kenkyusho

Makio Iida

Shoji Miura

Toshio Sakakibara

Yoshihiko Isobe

Takayuki Sugisaka

Hiroyuki Ban

Mitsuhiro Saitou

Mikimasa Suzuki

Makoto Ohkawa

Norihito Tokura

Hiroshi Fujimoto

Yasunori Taga

Hiroshi Maeda

Hiroshi Imai

Naoto Okabe

Yoshiaki Nakayama

Tetsuaki Kamiya

Osamu Ishihara

Tetsuo Fujii

Shoji Mizuno

Hisayoshi Fujikawa

Satoshi Shiraki

Kiyoshi Yamamoto

Takeshi Ohwaki

Yasuhiro Kitamura

Tadashi Shibata

Hideya Yamadera

Kenji Kohno

Tadashi Suzuki

Akitaka Murata

Masami Saito

Hirofumi Abe

Makoto Muto

Katsuyoshi Oda

Kanemitsu Terada

Keizou Kajiura

A semiconductor device is provided having a power transistor structure. The power transistor structure includes a plurality of first wells disposed independently at a surface portion of a semiconductor layer; a deep region having a portion disposed in the semiconductor layer between the first wells; a drain electrode connected to respective drain regions in the first wells; a source electrode connected to respective source regions and channel well regions in the first wells, such that either the drain electrode or the source electrode is connected to an inductive load; and a connecting member for supplying the deep region with a source potential, where the connecting member is configurable to connect to the drain electrode when the drain electrode is connected to the inductive load and to connect to the source electrode when the source electrode is connected to said inductive load.

Power MOS transistor for absorbing surge current

A semiconductor device having a thin film resistor which comprises at least chromium, silicon and nitrogen, and formed on a substrate with having a special ratio of the chemical composition, the semiconductor device having a characteristic such that variations of the resistance value thereof due to temperature variations can be effectively suppressed.

Semiconductor device having thin film resistor and method of producing same

A semiconductor device including a reduced surface field strength type LDMOS transistor which can prevent the breakdown of elements at channel formation portions when a reverse voltage is applied to its drain. A P well and an N well are formed in an N-type substrate to produce a double-well structure, with a source electrode being set to be equal in electric potential to the N-type substrate. The drift region of the N well has a dopant concentration to satisfy the so-called RESURF condition, which can provide a high breakdown voltage a low ON resistance. When a reverse voltage is applied to a drain electrode, a parasitic bipolar transistor comprising the N well, the P well and the N-type substrate develops to form a current-carrying path toward a substrate, so that the element breakdown at the channel formation portions is avoidable at the application of the reverse voltage.

Semiconductor device and manufacturing method thereof

A laser trimming is favorably performed by a strengthened laser beam energy. A level difference portion having a taper portion that is oblique with respect to the thicknesswise direction of a semiconductor substrate is formed at a surface of a semiconductor substrate. An insulating film is formed thereon and has its surface made flat, and then the thin film element is formed thereon. Thereafter, laser trimming is performed with respect to the thin film resistor. As a result, a state of interference between incident laser beam and reflected laser beam reflected from the interface between the semiconductor substrate and the insulating film is varied to thereby enable the production of a zone where laser beam energy is strengthened and a zone where laser beam energy is weakened.

Semiconductor device having oblique portion as reflection

In an insulated gate type field effect transistor and a manufacturing method of the same, a diffusion region is formed in a semiconductor substrate under an oxidizing atmosphere by thermal diffusion, and a first conductivity type semiconductor layer is formed on the semiconductor substrate by vapor-phase epitaxy after the formation of the diffusion region. Thereafter, the surface of the semiconductor layer is flattened, and a gate insulating film and a gate electrode are formed on the flattened semiconductor layer. Further, a well region as well as a source region are formed in the semiconductor layer to form an insulated gate type field effect transistor. As the surface of the semiconductor layer in which the insulated gate type field effect transistor is formed is flattened, even if the embedded region is formed in the wafer, the gate-source insulation withstand voltage characteristic can be prevented from being deteriorated.

Insulated gate type field effect transistor and method of manufacturing

A semiconductor device including a semiconductor substrate having a main surface. An insulating film is formed on the main surface of the semiconductor substrate. A semiconductor layer is placed on the insulating film. Side insulating regions extending from a surface of the semiconductor layer to the insulating film divide the semiconductor layer into element regions. The element regions are isolated from each other by the side insulating regions and the insulating film. The semiconductor substrate has a resistivity of 1.5 .OMEGA.cm or lower. A voltage at the semiconductor substrate is set to a given voltage.

Design for a semiconductor device having elements isolated by insulating

Even when a contact hole is formed before thin-film resistor formation, a contact area exposed in the contact hole is prevented from damaging. A semiconductor element is formed in a silicon semiconductor substrate and an oxide film is formed on the surface of the semiconductor substrate. Then, a contact hole is formed on the oxide film and moreover, a CrSiN film serving as a thin-film resistor and a TiW film serving as a barrier metal are formed on the oxide film. The TiW film is patterned by a mask and the CrSiN film is patterned through chemical dry etching. Finally, an Al electrode is formed on the semiconductor element and the CrSiN film through the contact hole and moreover a protective film is formed thereon.

Method for fabricating semiconductor device having thin-film resistor

A non-volatile memory cell having a structure having improved integration and simplified electrode wiring structure. The programmable non-volatile memory cell of the present invention adopts a mono-layer gate scheme to simplify the electrode wiring structure and to eliminate a current leakage problem of an insulating film between electrodes. A side and bottom of a semiconductor region, which is disposed directly below a capacity electrode section with a gate insulating film interposed therebetween that compose a control electrode, are isolated from another semiconductor region and semiconductor substrate by insulating films. Thus, a high programming control voltage which is not limited by a junction yield voltage between the semiconductor regions and semiconductor substrate may be applied. Due to that, an area of the capacity electrode section of a floating electrode may be considerably reduced.

Programmable non-volatile memory cell

A semiconductor device which can compatibly achieve the improvement of the withstand voltage and the integration degree. A PN junction between a buried collector region 3 and a collector withstand voltage region 4 is subjected to reverse bias, and a depletion layer in the PN junction reaches a side dielectric isolation region 9a which dielectrically isolates the side of the collector withstand voltage region 4. A circumferential semiconductor region 14 which is in adjacency to the collector withstand voltage with the side dielectric isolation region 9a therebetween has an electric potential that is approximate to that at a base region 5 rather than that at the buried collector region 3. As a result, the depletion layer is subjected to the effect of low electric potential from both the base region 5 and the circumferential semiconductor region 14. This mitigates electrostatic focusing in the vicinity of the corner parts between the sides of the base region 5 and the bottom thereof, restraining the avalanche breakdown there and improving the withstand voltage there.

High withstand voltage type semiconductor device having an isolation

A fuse fusible type semiconductor device capable of reducing energy required for fusing and a production method of the semiconductor device. In a semiconductor device equipped with a heat-fusible thin film resistor, the thin film resistor formed on a substrate 1 through an insulating film 2 is made of chromium, silicon and tungsten, and films 7 and 8 of a insulator including silicon laminated on the upper surface of the fusing surface, aluminum films 5 are disposed on both sides of the fusing surface and a barrier film 4. This semiconductor device is produced by a lamination step of sequentially forming a first insulating film 2, a thin film resistor 3, a barrier film 4 and an aluminum film 5 on a substrate 1 for reducing drastically fusing energy, an etching step of removing the barrier film 4 and the aluminum film 5 from the fusing region 31 of the thin film resistor 3, and an oxide film formation step of depositing the insulator including silicon films 7 and 8.

Semiconductor device equipped with a heat-fusible thin film resistor and

A semiconductor device is provided which makes a high withstand voltage bipolar transistor small and prevents deterioration in a switching speed of the transistor. A silicon oxide layer is formed on a silicon substrate, and a semiconductor island of one conductivity type which is isolated laterally by an isolation trench is formed on the silicon oxide layer. A silicon oxide film is formed on an outer periphery portion of the semiconductor island to bury the trench. In the semiconductor island, a bipolar transistor, namely a base region of the other conductivity type, is formed, and in the base region an emitter region of one conductivity type is formed and a collector region of one conductivity type is further formed. In the semiconductor island a diffusion region of the other conductivity type for extracting excessive carriers to which a constant electric potential is applied is further formed.

Dielectric isolated type semiconductor device provided with bipolar

A dielectric isolated type semiconductor device which can achieve a reduction in crystalline defects by means of a simple production process is provided. High-concentration regions are formed as active regions on a surface portion of an islandish semiconductor region which is isolated from an adjacent semiconductor region by means of an isolation trench. According to a first aspect of the present invention, an N type crystalline defect suppression region doped at a high concentration and deeper than the high-concentration regions is formed over the entire surface of an adjacent semiconductor region. According to a second aspect of the present invention, a high-concentration N type crystalline defect suppression region is provided on a surface portion of a P type high-concentration region is formed with identical structure and by an identical production process. By means of these N type regions, crystalline defects are reduced.

Dielectric isolated type semiconductor device

A thin film resistor on a semiconductor device may be laser trimmed while reducing the influence of film thickness of a passivation film formed on the thin film resistor. An underlying oxide film consisting of a BPSG film and a silicon oxide film is formed on an Si substrate. A silicon oxide film and a silicon nitride film are formed on the underlying film as a passivation film, and a silicon oxide film is formed on this assembly. The silicon oxide film contributes to controlling a variation of the laser energy absorption rate of a thin film resistor due to an uneven thickness of the silicon nitride film. Thus, it is possible to stabilize adjustment of the resistance value of the thin film resistor with a laser.

Semiconductor device with thin film resistor having reduced film

A method of preparing a patterned thin film resistor that is appropriately used in combination with semiconductor devices. The method comprises a thin film forming step comprising forming a thin film of a compound comprising at least one metal on an oxide film such as a silicon oxide film; a masking step comprising covering a desired area of the thin film by an organic material; a patterning step comprising converting to plasma a gas mixture comprising a fluorine compound gas and oxygen, and removing an area of the thin film, that is not covered by the organic material by exposing it to a gas containing activated fluorine by the plasma conversion; and a removing step comprising removing the organic material remaining on the desired area of the thin film.

Growing community of inventors

Ichinomiya, Japan

Makio Iida