Mitsumi Electric Company Ltd.

Makio Abe

Takatoshi Itagaki

Masato Aoki

Shu Hayashi

Junichi Kimura

Akira Ikeuchi

Fumihiro Inoue

A motor control circuit includes a control circuit configured to output a pulse width modulation signal for controlling a switching operation of an inverter circuit, the inverter circuit being configured to supply an alternating current power to a motor, and includes a speed-change detecting circuit configured to detect a change in a speed command signal and, output, in response to the change meeting and exceeding a predetermined limit, a signal indicating that the speed command signal has changed to the control circuit to cause the control circuit to change a duty cycle of the pulse width modulation signal, the speed command signal specifying a target value of a rotational speed of the motor.

Motor control circuit and motor controller

A motor control circuit includes a control circuit configured to control a switching operation of an inverter circuit, the inverter circuit being configured to supply an alternating current power to a motor, and includes a determination-information generating circuit configured to generate at least one determination value that conveys information on whether the motor malfunctions or deteriorates. The motor control circuit includes a determination circuit configured to determine whether the motor malfunctions or deteriorates based on the determination value to output, as an interrupt signal, a signal indicating that the motor malfunctions or deteriorates to the control circuit.

A semiconductor integrated circuit includes a central processing unitthe operation of which is stopped or slowed down in a sleep mode; an edge detection unitdetecting an edge of an interrupt signal supplied from the outside and generating an edge detection signal; and a data holding unitholding data supplied from the outside when the edge detection signal is received. The central processing unitreads the data held by the data holding unitafter returning from the sleep mode to an active mode in response to the interrupt signal.

Semiconductor integrated circuit

A communication circuit includes a sampling clock generating circuit generating a sampling clock signal having a frequency that is 'm' times greater than a bit rate of the communication data and containing 'n' pulses in each bit period of the communication data; and a sampling circuit sampling the communication data based on the sampling clock signal to obtain &#x201c;n&#x201d; sets of received data in each bit period of the communication data. The sampling clock generating circuit delays the sampling clock signal when a first one or more of the &#x201c;n&#x201d; sets of received data are different from a value of the rest of the &#x201c;n&#x201d; sets of received data, and advances the sampling clock signal when a value of a last one or more of the &#x201c;n&#x201d; sets of received data is different from a value of the rest of the &#x201c;n&#x201d; sets of received data.

Communication circuit and method of adjusting sampling clock signal

A delta-sigma AD converter circuit includes a plurality of registers to store plural data obtained by dividing data stored in the shift register and to hold the plural data in such a form that each of the plural data is readable independently of the others, wherein one or more of the plurality of registers store the pulse density modulated data stored in the shift register in response to the register store instruction signal, and the filtering unit reads the pulse density modulated data from one or more of the plurality of registers responsive to the mode in response to the read request signal.

Delta-sigma AD converter circuit and battery pack

An oscillator circuit includes a clock oscillator which outputs a main clock signal having an oscillating frequency switched between a high frequency and a low frequency in response to a frequency selection signal, and a frequency divider circuit which outputs a sub-clock signal having a divided frequency equivalent to a frequency division ratio of the oscillating frequency of the main clock signal, the frequency division ratio being switched in response to the frequency selection signal. The divided frequency of the sub-clock signal is predetermined for each of the high frequency and the low frequency to which the oscillating frequency is switched in response to the frequency selection signal.

Oscillator circuit

A fuel gauge circuit detects a residual quantity of a batteryand is disposed on a substratetogether with a protection circuitwhich protects charging/discharging of the battery. The fuel gauge circuit includes a voltage monitor terminal Tdisposed on a side facing a positive power-supply terminalof the substrate and connected to each of the positive power-supply terminaland a voltage sensordisposed in the circuit, a voltage through terminal Tdisposed on a side facing the protection circuit, opposite to the side facing the positive power-supply terminal, and connected to a voltage monitor terminal Tof the protection circuit, and a wiringdisposed within the circuit to connect the voltage monitor terminal Tof the fuel gauge circuit to the voltage through terminal T

Fuel gauge circuit and battery pack

A semiconductor integrated circuit device is disclosed that includes a signal processing unit having a nonvolatile memory and a detection unit; plural oscillation sources outputting plural oscillation signals; a selection control unit that selects one of the oscillation signals output by the oscillation sources according to a selection signal, and controls a transfer timing for transferring circuit setting information from the nonvolatile memory to the detection unit and an operations start timing for starting signal processing operations of the signal processing unit according to the selected oscillation signal.

Semiconductor integrated circuit device

A disclosed semiconductor integrated circuit device includes a selection circuit that is supplied with a first clock signal and a second clock signal, a selection signal, and a switching signal, and configured to select one of the first clock signal and the second clock signal according to the selection signal and to change the selected one of the first clock signal and the second clock signal to the other one of the first clock signal and the second clock signal according to the switching signal. The disclosed semiconductor integrated circuit device also includes an output fixing circuit configured to generate a pulse that is maintained at a high level or a low level during a certain period, to perform an OR operation on the output signal from the selection circuit and the generated pulse, and to output a result of the OR operation as the output clock signal.

Growing community of inventors

Tokyo, Japan

Makio Abe