Fujitsu Corporation

Fujitsu Semiconductor Limited

T. Hasegawa Co., Ltd.

Makiko Ito

Katsuhiro Yoda

Mitsuru Tomono

Hideo Miyake

Takahisa Suzuki

Takahiro Notsu

Hiromasa Yamauchi

Manabu Kubota

Atsuhiro Suga

Yasumoto Tomita

Yasuki Nakamura

Teruo Ishihara

Koichi Shirahata

Takashi Arakawa

Yamato Miyazawa

Yukihito Kawabe

Kazuhiro Nomoto

Shunsuke Inenaga

Wataru Kanemori

Keisuke Yoshikawa

Hiroya Uehara

An information processing apparatus that performs deep learning using a neural network includes a memory, and an arithmetic processing device that performs a process for layers of the neural network in a predetermined direction. The process for the layers includes: pre-determining a decimal point position of a fixed-point number of an intermediate data obtained by an operation of each of the layers; performing the arithmetic operation for each layer with the pre-determined decimal point position to obtain the intermediate data and acquiring first statistical information of a distribution of bits of the intermediate data; determining a decimal point position of the intermediate data based on the statistical information; and performing the arithmetic operation for each layer with the determined decimal point position again when the difference of the determined decimal point position and the pre-determined decimal point position is greater than a threshold value.

Training program, training method, and information processing apparatus

An information processor includes a memory; and a processor coupled to the memory and the processor configured to: acquire first statistical information about distribution of most significant bit position that is not a sign or least significant bit position that is not zero for each of a plurality of first fixed-point number data, the data being a computation result of the computation in the first layer; execute computation on a plurality of output data of the first layer according to a predetermined rule, in the computation in the second layer; and acquire second statistical information based on the predetermined rule and the first statistical information, and determine a bit range for limiting a bit width when a plurality of second fixed-point number data, the data being a computation result of the computation in the second layer, are stored in a register, based on the second statistical information.

Information processor, information processing method, and storage medium

An information processing apparatus includes a processor including a first operation circuit that executes a product-sum operation, a second operation circuit that executes a certain operation, and a resister. The processor executes a first operation including the certain operation in a first layer in a neural network. The processor executes the first operation by a second method of calculating the certain operation by the second operation circuit, in a case where second operation time necessary for the first operation when the certain operation is executed by the second operation circuit is less than memory transfer time. Or the processor executes the first operation by a first method of calculating the certain operation by an approximate calculation by the first operation circuit, in a case where first operation time necessary for the first operation when executed by the first method is less than the memory transfer time.

Information processing apparatus, neural network program, and processing method for neural network

An arithmetic processing apparatus includes: a memory that stores, when a training of a given machine learning model is repeatedly performed in a plurality of iterations, an error of a decimal point position of each of a plurality of fixed-point number data obtained one in each of the plurality of iterations, the error being obtained based on statistical information related to a distribution of leftmost set bit positions for positive number and leftmost unset bit positions for negative number or a distribution of rightmost set bit positions of the plurality of fixed-point number data; and a processor coupled to the memory, the processor being configured to: determine, based on a tendency of the error in each of the plurality of iterations, an offset amount for correcting a decimal point position of fixed-point number data used in the training.

Arithmetic processing apparatus, control method, and non-transitory computer-readable recording medium having stored therein control program

A compound represented by the following formula (1): 

Pyrrole compound, method of making same, and aroma composition, food, drink and cosmetics containing same

An operation processing device includes: a memory; and a processor coupled to the memory and configured to: acquire statistical information on distribution of bits in fixed point number data after execution of an instruction on the fixed point number data; and update a decimal point position of the fixed point number data.

Operation processing device, information processing device, and information processing method

An information processing apparatus includes a memory and a processor coupled to the memory. The processor acquires statistical information on a distribution of bits in floating point number data after executing an instruction on the floating point number data, and converts the floating point number data to fixed point number data.

Information processing apparatus, information processing method, and recording medium

An operation processing apparatus includes a memory and a processor coupled to the memory. The processor executes an operation according to an operation instruction, acquires statistical information for a distribution of bits in fixed point data after an execution of an operation for the fixed point data according to an acquisition instruction, and outputs the statistical information to a register designated by the acquisition instruction.

Operation processing apparatus, information processing apparatus and information processing method

An arithmetic processor includes a plurality of arithmetic circuits that individually execute an arithmetic operation for fixed point data; and at least one of first and second statistical information is acquired regarding a plurality of fixed point data that are results of arithmetic operation executed by the plurality of arithmetic circuits. The first statistical information is obtained by accumulating a bit pattern, which is obtained by setting a flag bit to each of bit positions corresponding to a range from a least-significant-bit position to a highest-order bit position for each of the digits corresponding to the bit positions, and the second statistical information is obtained by accumulating a bit pattern, which is obtained by setting a flag bit to each of bit positions corresponding to a range from the position of the sign bit to a lowest-order-bit position for each of the digits corresponding to the bit positions.

Arithmetic processor, arithmetic processing apparatus including arithmetic processor, information processing apparatus including arithmetic processing apparatus, and control method for arithmetic processing apparatus

A processor includes: a plurality of processor cores; and an internal memory configured to be accessed from the plurality of processor cores, wherein an arithmetic circuit provided in any of the plurality of processor cores includes: a plurality of first registers provided in a first stage of the arithmetic circuit, a regular addition circuit including a first adder and a second register, the first adder being configured to add a plurality of outputs of the plurality of first registers, the second register being configured to be provided in a second stage and latch an output of the first adder, an overtaking addition circuit including a second adder, the second adder being configured to add a plurality of outputs of the plurality of first registers, and a synthesis circuit including a third adder and a third register.

Processor, information processing apparatus and operation method for processor

A processor accesses memory storing a compressed instruction sequence that includes compression information indicating that an instruction that with respect to the preceding instruction, has identical operation code and operand continuity is compressed. The processor includes a fetcher that fetches a bit string from the memory and determines whether the bit string is a non-compressed instruction, where if so, transfers the given bit string and if not, transfers the compression information; and a decoder that upon receiving the non-compressed instruction, holds in a buffer, instruction code and an operand pattern of the non-compressed instruction and executes processing to set to an initial value, the value of an instruction counter that indicates a count of consecutive instructions having identical operation code and operand continuity, and upon receiving the compression information, restores the instruction code based on the instruction code held in the buffer, the instruction counter value, and the operand pattern.

Compressing detected current and preceding instructions with the same operation code and operand patterns

A processor, which executes m number of arithmetic operations in parallel, executes a partial sum instruction which takes an i-th to (i+m&#x2212;1)-th elements of an input data series as input elements, so as to obtain first vector data, executes the partial sum instruction which takes a (i+x)-th to (i+x+m&#x2212;1)-th elements of the input data series as the input elements, so as to obtain second vector data, and performs operations to subtract the p-th element of the first vector data and add the p-th element of the second vector data from and to a sum of the i-th to (i+x&#x2212;1)-th elements of the input data series in parallel for each of the 0-th to (m&#x2212;1)-th elements, so as to calculate sums of elements for m sections different from each other in parallel, and moving average processing to calculate a moving average from the sums of elements of the sections.

Moving average processing in processor and processor

A method of generating a parallelized program includes calculating an execution order of vertices of a degenerate program dependence graph, generating basic blocks by consolidating vertices including neither branching nor merging, generating procedures each corresponding to a respective one of the vertices, and generating a procedure control program by arranging an instruction to execute a first procedure after an instruction to wait for output data transfer from a second procedure for a dependence relation crossing a border between the basic blocks, generating an instruction to register a dependence relation that a third procedure has on output data transfer from a fourth procedure for a dependence relation within one of the basic blocks, and generating an instruction to perform a given data transfer directly from procedure to procedure for each of a data transfer within one of the basic blocks and a data transfer crossing a border between the basic blocks.

Generation of parallelized program based on program dependence graph

An information processing apparatus sequentially selects a function whose execution frequency is high as a selected function that is to be stored in an internal memory, in a source program having a hierarchy structure. The information processing apparatus allocates the selected function to a memory area of the internal memory, allocates a function that is not the selected function and is called from the selected function to an area close to the memory area of the internal memory, and generates an internal load module. The information processing apparatus allocates a remaining function to an external memory coupled to a processor and generates an external load module. Then, a program executed by the processor having the internal memory is generated.

Method for generating program and method for operating system

A dependent element group which is invertibly contractible is found by using program analysis information including a plurality of dependent elements representing dependent relationships of statement and control, the statement and the control being included in a program. Next, a program dependence graph in which dependent elements are made to be contracted is generated by contracting the found dependent element group. The number of vertices and the number of edges of the program dependence graph are reduced by the contraction of the dependent elements, so that a program dependence graph with a rough granularity can be generated. As a result, a calculation amount (calculation time) necessary for optimization processing such as parallel processing of the program can be reduced. That is, by generating the contracted program dependence graph having invertibility, it is possible to realize the analysis and optimization of large-scale software in a realistic time.

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Kawasaki, Japan

Makiko Ito