Intel Corporation

Makaram Raghunandan

Wajdi K Feghali

Vinodh Gopal

Gilbert M Wolrich

Kirk S Yap

Srinivas Chennupaty

Shay Gueron

Martin Guy Dixon

Michael E Kounavis

Brent Ralph Boswell

Rajendra S Yavatkar

Yogesh Bansal

Stephanie L Hirnak

Shou C Chen

Dave Edwards

Geoffrey R Gustafson

A flexible instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a 'one round' pass for encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.

Flexible architecture and instruction for advanced encryption standard (AES)

In one embodiment, the present invention includes a processor having logic to perform a round of a cryptographic algorithm responsive to first and second round micro-operations to perform the round on first and second pairs of columns, where the logic includes dual datapaths that are half the width of the cryptographic algorithm width (or smaller). Additional logic may be used to combine the results of the first and second round micro-operations to obtain a round result. Other embodiments are described and claimed.

Method and apparatus for performing cryptographic operations

In one embodiment, the present disclosure provides a method capable of processing a variety of different operations. A method according to one embodiment may include loading configuration data from a shared memory unit into a hardware configuration register, the hardware configuration register located within circuitry included within a hardware accelerator unit. The method may also include issuing a command set from a microengine to the hardware accelerator unit having the circuitry. The method may additionally include receiving the command set at the circuitry from the microengine, the command set configured to allow for the processing of a variety of different operations. The method may further include processing an appropriate operation based upon the configuration data loaded into the hardware configuration register. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.

Method for processing multiple operations

Techniques are described herein that can be used to access entries in a packed table. An unpacked table includes empty and filled elements. Filled elements can be accumulated and included in a packed table. An element in the packed table can be accessed by considering the location the element would have been located in the unpacked table. The location can be used to determine the location of the element in the packed table.

Techniques for accessing a table

According to some embodiments, execution information is received from a first development tool. Execution information is also received from a second development tool. Based on the first execution information and the second execution information, operation of the first development tool may be controlled. According to some embodiments, the first and second development tools are associated with different processor architectures.

System development tool

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Northboro, MA, United States of America

Makaram Raghunandan