Motorola Corporation

National Scientific Corporation

Other

Sirf Technology, Inc.

Majid M Hashemi

El-Badawy Amien El-Sharawy

Saied N Tehrani

Jonathan K Abrokwah

Jenn-Hwa Huang

Vijay K Nair

Erik E Anderson

Daniel Babitch

Kurt W Eisenbeiser

Stephen P Rogers

Sung P Pack

Yang Wang

Ismail H Ozguc

Patricia A Norton

Kazim Sevens

Vernon Patrick O'Neil, Ii

Farideh Nikpourian

A radio frequency integrated circuit for a global positioning system (GPS) application mixes radio frequency GPS signals from an external source with a predetermined intermediate frequency that is less than 4f. In one embodiment, the intermediate frequency is selected to be 1.5f. An intermediate frequency filter then band-limits the intermediate frequency GPS signals, rolling off at a frequency in the vicinity of 2.5 MHz to achieve substantial attenuation at 3.5-4.0 MHz. An automatic gain control circuit amplifies the filtered intermediate frequency GPS signals to proper voltage levels. The amplified intermediate frequency GPS signals is then digitized by an analog-to-digital converter at a predetermined sampling rate more than twice the intermediate frequency to provide samples of a predetermined number of bits, which are then provided for base band processing by a general purpose microprocessor over an industry-standard serial bus.

GPS front end having an interface with reduced data rate

A receiver () includes an IF filter () and a nearby process-variant circuit () formed on a common semiconductor substrate (). The actual center frequency of the IF filter () is determined by resistors () and capacitors () exhibiting imprecise values and is unlikely to equal a nominal center frequency. The process-variant circuit () includes a test resistor () and test capacitor () formed using the same resistor-forming and capacitor-forming processes used to form the IF filter resistors (70, 74) and capacitors (). In response a test signal () from the process-variant circuit () and a reference signal () from a process-invariant circuit (), a tuning parameter for a tunable local oscillator () is determined so that a local oscillation signal () will exhibit a frequency which, when mixed with an RF signal () yields an IF signal () at the actual center frequency of the IF filter ().

Communications receiver with integrated IF filter and method therefor

A heterojunction bipolar transistor ( ) is provided with a silicon (Si) base region ( ) that forms a semiconductor junction with a multilayer emitter ( ) having a thin gallium arsenide (GaAs) emitter layer ( ) proximate the base region ( ) and a distal gallium phosphide (GaP) emitter layer ( ). The GaAs emitter layer ( ) is sufficiently thin, preferably less than 200 &angst;, so as to be coherently strained. In one embodiment, the GaP emitter layer includes a doped region ( ) which serves as the emitter and a non-doped region ( ) on which the intrinsic portion of the transistor ( ) is formed.

Vertical heterojunction bipolar transistor

A static RAM memory cell (,) uses cross-coupled enhancement mode, N-channel MOS drive transistors (,) to form a bistable flip-flop. A load circuit (,) couples between I/O ports (,) of the drive transistors (,) and Vcc. For each drive transistor (,), the load circuit includes a depletion mode, N-channel MOS load transistor (,) and a forward biased tunnel diode (,). The drain and gate of the load transistor (,) couple across the anode and cathode of the tunnel diode (,) so that the forward voltage (V,) of the tunnel diode (,) controls the V,transfer curve (,) of the load transistor. The tunnel diode (,) may be formed at a junction between a mono-crystalline silicon layer (,) at a region (,) which also serves as a source or drain of a transistor (,) and a poly-crystalline silicon layer (,). The poly-crystalline silicon layer (,) also serves as a non-metallic, conductive interconnection (,) to save space.

Electronic semiconductor circuit which includes a tunnel diode

A monolithic inductor (,&prime;) is formed over a silicon or other substrate (,). The inductor (,&prime;) includes at least one coil (,) arranged so that its axis (,) is parallel to the substrate (,). Other inductive features, such as other coils (,) or planar spirals (,) are arranged in series with the coil (,) to guide magnetic flux lines away from the substrate (,). In one embodiment, a common thin film coil core (,) made from a magnetic material is provided for two coils (,). The coil core (,) provides a continuous magnetic material flux path through the two coils (,). In another embodiment, an axis (,) of the coil (,) is located between the plane in which two spirals (,) are located and the substrate (,) to guide magnetic flux lines (,) away from the substrate (,).

Monolithic inductor with magnetic flux lines guided away from substrate

A heterojunction bipolar transistor (,) is provided with a silicon (Si) base region (,) that forms a semiconductor junction with a multilayer emitter (,) having a thin gallium arsenide (GaAs) emitter layer (,) proximate the base region (,) and a distal gallium phosphide emitter layer (40). The GaAs emitter layer (,) is sufficiently thin, preferably less than 200 &angst;, so as to be coherently strained.

Method of forming heterojunction bipolar transistor having wide bandgap, low interdiffusion base-emitter junction

A static RAM memory cell (30) uses cross-coupled enhancement mode, N-channel MOS drive transistors (36) to form a bistable flip-flop. A load circuit (34) couples between I/O ports (40) of the drive transistors (36) and Vcc. For each drive transistor (36), the load circuit includes a depletion mode, N-channel MOS load transistor (54) and a forward biased tunnel diode (32). The drain and gate of the load transistor (54) couple across the anode and cathode of the tunnel diode (32) so that the forward voltage (V.sub.f) of the tunnel diode (32) controls the V.sub.gs transfer curve (56) of the load transistor.

Static memory cell with load circuit using a tunnel diode

A monolithic inductor (20, 20') is formed over a silicon or other substrate (22). The inductor (20, 20') includes at least one coil (62, 78) arranged so that its axis (58) is parallel to the substrate (22). Other inductive features, such as other coils (64, 70, 72) or planar spirals (74, 76) are arranged in series with the coil (62, 78) to guide magnetic flux lines away from the substrate (22). In one embodiment, a common thin film coil core (60) made from a magnetic material is provided for two coils (62, 64). The coil core (60) provides a continuous magnetic material flux path through the two coils (62, 64). In another embodiment, an axis (58) of the coil (78) is located between the plane in which two spirals (74, 76) are located and the substrate (22) to guide magnetic flux lines (82) away from the substrate (22).

A heterojunction bipolar transistor (20) is provided with a silicon (Si) base region (34) that forms a semiconductor junction with a multilayer emitter (38) having a thin gallium arsenide (GaAs) emitter layer (36) proximate the base region (34) and a distal gallium phosphide emitter layer (40). The GaAs emitter layer (36) is sufficiently thin, preferably less than 200 .ANG., so as to be coherently strained.

Heterojunction bipolar transistor having wide bandgap, low

A high power heterojunction field effect transistor comprising a first barrier layer including a semiconductor material having a band gap, a second barrier layer including a semiconductor material having a band gap, a channel layer including a semiconductor material having a band gap narrower than the band gaps of the material included in the first barrier layer and the second barrier layer and sandwiched therebetween and an interface layer sandwiched between the channel layer and the first barrier layer.

High power HFET with improved channel interfaces

A heterostructure field effect transistor and method including at least one passivation layer (20) and at least one etch stop layer (22). Enhancement, depletion and combined devices with both enhancement mode and depletion mode devices are possible with minor process variations. Refractory gate (40) and non-gold refractory ohmic contact (52) metallization combined with other features allows non-liftoff metal patterning.

Refractory gate heterostructure field effect transistor

A high frequency transistor including a heavily doped first current carrying layer positioned on a substrate and a semi-insulating layer of LTGaAs epitaxially grown on the first layer. The semi-insulating layer is etched, using a layer of AlAs as an etch stop, to define an active region and a first current carrying electrode is grown on the exposed first layer in the active region. A control layer is grown on the semi-insulating layer and the first current carrying electrode, and a second current carrying electrode is grown on the control layer. External contacts are formed on the first current carrying layer, the control layer, and the second current carrying electrode.

High frequency semiconductor transistor

A process of fabricating submicron features including depositing a gate metal layer on a substrate and forming a first etchable layer of material on the metal layer to define a first sidewall. A second etchable layer is deposited on the structure so as to define a second sidewall. The second etchable layer is etched so as to leave only the second sidewall and the first etchable layer is removed. The metal layer is etched using the second sidewall as an etch mask to form a submicron feature. The width of the feature depends upon the thickness of the metal layer.

Methods of fabrication of submicron features in semiconductor devices

A method of fabricating a self-aligned FET having a semi-insulating substrate of GaAs or InP with a conductive channel formed either by doping the surface or an epitaxially grown channel by molecular beam epitaxy or metalorganic vapor phase epitaxy in the substrate adjacent the surface. Forming a high temperature stable LaB.sub.6 /TiWN 'T-shaped' Schottky gate contact on the substrate surface, which is used for source and drain ohmic region implants into the substrate adjacent to the surface and self-aligned to the 'T-shaped' gate, with source and drain ohmic contacts also self-aligned with respect to the gate.

Method of fabricating self-aligned FET structure having a high

A method of fabricating high breakdown voltage MESFETs forming a conduction channel in a GaAs substrate adjacent the surface, forming high temperature stable source and drain ohmic contacts and a Schottky gate contact on the surface of the substrate in overlying relationship to the channel and in spaced relationship, and depositing a layer of low temperature GaAs passivation material over the substrate surface and the source, drain and gate contacts. Openings are then etched in the passivation material for contacting the source, drain and gate contacts.

Growing community of inventors

Tempe, AZ, United States of America

Majid M Hashemi