Siemens Aktiengesellschaft

Siemens Ag Osterreich

Majid Ghameshlu

Herbert Taucher

Friedrich Eppensteiner

Karlheinz Krause

Martin Matschnig

Bernhard Fischer

Thomas Hinterstoisser

Wolfgang Kainrath

Johann Deix

Stephan Knecht

Ulrich Hahn

A system and method for the predictive maintenance of electronic components that includes sensors at at least one position via which present values of system parameters, such as temperature and voltage, and a signal propagation time at the at least one position are determined, where values of the system parameters and the signal propagation time presently determined by the sensors are retrieved by a central monitoring unit, an individual valid limit value is determined for the signal propagation time at each of the at least one position via the central monitoring unit based on the presently determined values of the system parameters, and the presently determined signal propagation time at each of the at least one position is compared with the associated valid limit value, and a notification is sent to a superordinate level, if the signal propagation time exceeds the limit value to trigger replacement of the electronic component.

Method and system for predictive maintenance of integrated circuits

A method for adjusting a pull resistor on a contact terminal of an electronic module arranged on a printed circuit board, in particular an ASIC, after initiating a restart of the electronic module which, during a run-up process, moves the electronic module from a switched-off state into a switched-on state, wherein after initiating a restart during the run-up process from a partial circuit arranged on the electronic module and operationally ready during the run-up process, adjustment information relating to a desired adjustment of the pull resistor is retrieved from a storage unit arranged on the printed circuit board outside of the electronic module and transmitted via a contact line between the electronic module and the storage unit, where the run-up process of the electronic module is only completed after successful adjustment of the respective pull resistor based on basis the retrieved adjustment information.

Method for adjusting pull resistors of an electronic module

A circuit arrangement and method for temporally limiting and separating access between at least one master unit and at least one slave unit via a network-on-a-chip bus system in a system-on-a-chip, wherein the access between the at least one master and slave units is implemented via communication paths defined by bus interfaces, where within the circuit arrangement, the network-on-a-chip bus system is expanded by an adaptation unit that includes an access manager and a complementary logic for the bus interfaces, where the adaptation unit and the bus interfaces are then controlled by the access manager via the complementary logic using a communication plan such that access between the master and slave units via the communication paths specified by bus interfaces is performed in accordance with the temporal requirements of the communication plan so that time-controlled systems can be implemented simply using commercially obtainable standard bus systems.

Method and circuit arrangement for temporally limiting and separately accessing a system on a chip

A method for protecting an integrated circuit against unauthorized access to key registers, wherein functions and/or applications of the integrated circuit are unlocked and/or activated via data stored in key registers, such as during the start-up of the integrated circuit and/or during ongoing operation, where if such a key register is accessed, the data word used to perform the access is compared with specified key data, and if access via a data word deviating from the specified key data is detected, the access is marked as unauthorized, the access marked as unauthorized is then recorded and evaluated, and after the analysis, appropriate protective measures are triggered to prevent further unauthorized access such that a key register method for protecting sensitive data is expanded in a simple manner and hacker attacks are quickly detected and thwarted.

Method for protecting an integrated circuit against unauthorized access

A circuit arrangement and method for securing an integrated electronic circuit against scans of an address space, wherein the circuit arrangement has at least one master unit and at least one slave unit interconnected via a bus system for access of the master unit to the slave unit, and addresses are used from an address space that is allocated and used in accordance with functionalities of the integrated electronic circuit, where a defense slave unit is connected to the bus system, access to unused address regions of the address space are forwarded to the defense slave unit, the access is analyzed and evaluated by the defense slave unit and depending on an analysis result and the respective access type, defensive measures are triggered, such that address space scans are interrupted or a potential scan result is rendered useless in a simple manner.

Method and circuit arrangement for protecting against scanning of an address space

An IC including duplicated primary components which can be operated microsynchronously has at least one synchronization device for synchronizing asynchronous signals to the primary clock. An asynchronous signal intended for the primary components is routed via the synchronization device, synchronized and supplied to the inputs of the primary components. With duplicated asynchronous components, an output signal from just one asynchronous component is synchronized and is supplied to the primary components.

Integrated circuit including duplicated synchronous and asynchronous components

The present invention, in addition to the number of connections required for the specified functions of an ASIC, provides an application specific module ASIC that has additional connections as spares for subsequent modification. Buffers, boundary scan devices and, possibly, basic logic function, are reserved for the additional connections, which may be arranged in a geometrically uniform distribution and which are intended as inputs or as outputs. In the event of a redesign, in particular in the event of only minor design corrections, the effort development costs and time is considerably reduced.

Low redesign application-specific module

A processor device includes a clock generation unit, a processor unit, a main memory, a processor bus, and also a bus control device having an interface for a crossover bus to at least one further processor device. The bus control device monitors processor device data access through the processor bus, interchanges signals concerning data access through the crossover bus, evaluates them and outputs an error signal based on the evaluation result. In a processor system including at least two processor devices connected to one another through the crossover bus, the processor units are started in synchronism. The bus control devices in the processor devices interchange signals through the crossover bus upon each data access operation by the processor units, and output an error signal if there is no correspondence. If there is an error in one processor device, operation of the processor system is continued on the other processor device or devices.

Duplicable processor device

An integrated circuit having at least two clock systems in which the appropriate clock signal, starting from a clock input, can be forwarded through clock trees to individual switching elements or switching blocks. In this arrangement, each clock tree has an associated controlled switch which, for selected operating states, can be used to apply a single common clock signal to the clock trees, where at least a first clock tree has a PLL unit connected upstream of it, and an output of this clock tree is connected to an input of the PLL unit in order to form a phase locked loop, and the switches are actuated in selected operating states such that the common clock signal is supplied to a last clock tree, and an output of this clock tree is connected to the other input of the PLL unit for the at least first clock tree.

Integrated circuit comprising at least two clock systems

An integrated electronic module which is equipped with at least one hardware error infeed for testing purposes and which includes a number of terminals whereby the error infeed is controlled with a control logic. The control logic includes at least one terminal as data input for command signals at the control logic as well as an error control output which is connected to a signal input of the error infeed. The control logic decodes the command signals entered via the data input, derives commands for error control therefrom and gives signals to the error control output corresponding to these commands. The control logic may be constructed as part of a boundary scan test logic of the module.

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Vienna, Austria

Majid Ghameshlu