Other

Lsi Logic Corporation

Lsi Corporation

Deweyvision Corp.

Mips Tech Limited

Majid Bemanian

Farhang Yazdani

William D Scharf

Narayanan Raman

Aaron Malcolm Peddle

Gary Scott Delp

George Wayne Nation

Lawrence Henry Hudepohl

John N Fryar, Iii

Bruce L Entin

A data processing system for matching video content implements obtaining first video footage that includes a plurality of first video frames of a first video clip; obtaining second video footage that includes a plurality of second video frames; analyzing the first video footage and the second video footage to generate a plurality of first fingerprints representing each frame of the plurality of first video frames and a plurality of second fingerprints representing the second video frames; comparing the first fingerprints to the second fingerprints to identify one or more candidate clip matches for the first video clip in the second video footage; selecting a best match for the first video clip in the second video footage from the one or more candidate clip matches for the first video clip; and presenting the best match for the first video clip on a user interface.

Techniques for adaptive frame-based clip matching

A data processing system for generating a fingerprint of an image implements obtaining a first digital image; determining a first fingerprint for the first digital image comprising a first coarse-grain fingerprint element and a first fine-grain fingerprint element by determining the first coarse-grain component based on the first digital image; determining the first fine-grain component based on the first digital image; and generating the first fingerprint by combining the first coarse-grain component with the first-fine grain component; obtaining a second fingerprint for a second digital image, the second fingerprint comprising a second coarse-grain component and a second fine-grain component; comparing the first fingerprint with the second fingerprint to determine a similarity score; and performing one or more actions responsive to the similarity score equaling or exceeding a similarity threshold.

Techniques for adaptive frame-based clip matching and fingerprinting

Techniques are disclosed for processor synchronization within a reconfigurable computing environment for processor array redundancy. Processing elements are configured within a reconfigurable fabric to implement two or more redundant processors, where the two or more redundant processors are enabled for coincident operation. An agent is loaded on each of the two or more redundant processors, where the agent performs a function requiring data validation. The agent is fired on each of the two or more redundant processors to commence coincident operation. The coincident operation can include a lockstep operation. An output data result from each of the two or more redundant processors is compared to enable a data validation result. The data validation result is propagated. The propagating the data validation result can be based on comparing valid output data or can be based on comparing invalid output data.

Fail-safe semi-autonomous or autonomous vehicle processor array redundancy which permits an agent to perform a function based on comparing valid output from sets of redundant processors

An embodiment of this invention uses a massive parallel interconnect fabric (MPIF) at the flipped interface of a core die substrate (having the core logic blocks) and a context die (used for in circuit programming/context/customization of the core die substrate), to produce ASIC-like density and FPGA-like flexibility/programmability, while reducing the time and cost for development and going from prototyping to production, reducing cost per die, reducing or eliminating NRE, and increasing performance. Other embodiments of this invention enable debugging complex SoC through large contact points provided through the MPIF, provide for multi-platform functionality, and enable incorporating FGPA core in ASIC platform through the MPIF.

Massively parallel interconnect fabric for complex semiconductor devices

An embodiment of this invention uses a massive parallel interconnect fabric (MPIF) at the flipped interface of a core die substrate (having the core logic blocks) and a context die (used for in circuit programming/context/customization of the core die substrate), to produce ASIC-like density and FPGA-like flexibility/programmability, while reducing the time and cost for development and going from prototyping to production, reducing cost per die, reducing or eliminating NRE, and increasing performance. Other embodiments of this invention enable debugging complex SoC through large contact points provided through the MPIF, provide for multi-platform functionality, and enable incorporating FGPA core in ASIC platform through the MPIF. Various examples are also given for different implementations.

A partially manufactured semiconductor chip comprising a slice and a number of shells is a template for a communication and networking chip. The slice has a number of I/O ports, blocks, and PHYs. The hardmac PHYs are established to correspond to a high speed data transmission protocol. The interior of the template comprises logic gate arrays and configurable memory. Once particular protocols of data receipt and transmission are selected, the logic gate arrays and configurable memory can be programmed and otherwise configured to develop protocol layers for data networking and communication.

Flexible template having embedded gate array and composable memory for integrated circuits

A time division media access controller for use with a multi-port data switch and a method of controlling media access. In one embodiment, the time division media access controller includes a time division receive engine, a time division transmit engine and a time division arbiter coupled to the time division receive and transmit engines. The time division receive engine accepts data from a plurality of data ports and the time division transmit engine provides data to a plurality of data ports. The time division arbiter controls states of the time division receive and transmit engines based on throughput requirements of the data. In preferred embodiments, the time division media access controller complies with the IEEE 802.3 ethernet standard.

Time division media access controller and method of operation thereof

An integrated circuit (IC) and a method of manufacturing an integrated circuit suited for a particular application. In one embodiment, the IC includes: (1) at least two interfaces, (2) a programmable gate array (PGA) coupled to the at least two interfaces for communicating data therebetween and, optionally (3) a field-programmable gate array (FPGA) coupled to and configured to cooperate with the PGA to adapt the IC to a particular surrounding environment.

Integrated circuit having integrated programmable gate array and method of operating the same

An integrated circuit (IC) and a method of manufacturing an integrated circuit suited for a particular application. In one embodiment, the IC includes at least two interfaces, a field-programmable gate array (FPGA) and a programmable gate array (PGA). The FPGA has a configuration memory associated therewith and is coupled to the at least two interfaces for communicating data therebetween. The PGA is coupled to and configured to cooperate with the FPGA to adapt the IC to a particular surrounding environment.

Growing community of inventors

Pleasanton, CA, United States of America

Majid Bemanian