Xilinx, Inc.

Maithilee Rajendra Kulkarni

Dinesh D Gaitonde

Matthew H Klein

Chirag Ravishankar

Aashish Tripathi

Abhishek Kumar Jain

Himanshu Verma

Ashit Debnath

A 3D device includes a first semiconductor chip and a second semiconductor chip stacked vertically. The first semiconductor chip includes a first plurality of tiles. The second semiconductor chip includes a second plurality of tiles. A bus electrically couples each of the first plurality of tiles to a corresponding one of the second plurality of tiles based on assignments of the first plurality of tiles and the second plurality of tiles to tile-to-tile pairs that define a minimized sum of bus delays among each possible tile-to-tile pairs. In each tile-to-tile pair, a net electrically couples each of a first plurality of pins to a corresponding one of a second plurality of pins based on assignments of the first plurality of pins to the second plurality of pins that define a minimized sum of net delays among each possible pin-to-pin pairs.

3D stacked device having improved data flow

Embodiments herein describe assigning integrated circuits with defects as variants of the integrated circuit design. Each variant can deactivate different circuitry in the integrated circuit design. A location of the defect can be matched to a variant that has a deactivated region that covers the defect. The integrated circuit can then be assigned to that variant.

Software defined device variants

Growing community of inventors

Santa Clara, CA, United States of America

Maithilee Rajendra Kulkarni